參數(shù)資料
型號(hào): PIC24HJ64GP502-I/SO
廠商: Microchip Technology
文件頁數(shù): 19/84頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 64K 28SOIC
標(biāo)準(zhǔn)包裝: 27
系列: PIC® 24H
核心處理器: PIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: CAN,I²C,IrDA,LIN,PMP,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲(chǔ)器容量: 64KB(22K x 24)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b/12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 648 (CN2011-ZH PDF)
配用: AC164339-ND - MODULE SKT FOR PM3 28SOIC
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
DS70152H-page 26
2010 Microchip Technology Inc.
4.2.6
READC COMMAND
The READC command instructs the programming
executive to read N Configuration registers or Device
ID registers, starting from the 24-bit address specified
by Addr_MSB and Addr_LS. This command can only
be used to read 8-bit or 16-bit data.
When this command is used to read Configuration
registers, the upper byte in every data word returned by
the programming executive is 0x00 and the lower byte
contains the Configuration register value.
Expected Response (4 + 3 * (N 1)/2 words
for N odd):
0x1100
2 + N
Configuration register or Device ID Register 1
...
Configuration register or Device ID Register N
4.2.7
READP COMMAND
The READP command instructs the programming
executive to read N 24-bit words of code memory,
starting from the 24-bit address specified by Addr_MSB
and Addr_LS. This command can only be used to read
24-bit data. All data returned in the response to this
command uses the packed data format described in
Expected Response (2 + 3 * N/2 words for N even):
0x1200
2 + 3 * N/2
Least significant program memory word 1
...
Least significant data word N
Expected Response (4 + 3 * (N 1)/2 words
for N odd):
0x1200
4 + 3 * (N 1)/2
Least significant program memory word 1
...
MSB of program memory word N (zero padded)
15
12 11
8 7
0
Opcode
Length
N
Addr_MSB
Addr_LS
Field
Description
Opcode
0x1
Length
0x3
N
Number of 8-bit Configuration registers
or Device ID registers to read
(maximum of 256).
Addr_MSB
MSB of 24-bit source address.
Addr_LS
Least Significant 16 bits of 24-bit
source address.
Note:
Reading unimplemented memory will
cause the programming executive to
reset. Please ensure that only memory
locations present on a particular device
are accessed.
15
12 11
8 7
0
Opcode
Length
N
Reserved
Addr_MSB
Addr_LS
Field
Description
Opcode
0x2
Length
0x4
N
Number of 24-bit instructions to read
(maximum of 32768).
Reserved
0x0
Addr_MSB
MSB of 24-bit source address.
Addr_LS
Least Significant 16 bits of 24-bit
source address.
Note:
Reading unimplemented memory will
cause the programming executive to
reset. Please ensure that only memory
locations present on a particular device
are accessed.
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