參數(shù)資料
型號: PIC24HJ64GP510A-I/PF
廠商: Microchip Technology
文件頁數(shù): 55/84頁
文件大小: 0K
描述: IC PIC MCU FLASH 64KB 100-TQFP
標(biāo)準(zhǔn)包裝: 90
系列: PIC® 24H
核心處理器: PIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: CAN,I²C,IrDA,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 85
程序存儲器容量: 64KB(22K x 24)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 32x10b/12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 648 (CN2011-ZH PDF)
配用: 876-1004-ND - PIC24 BREAKOUT BOARD
2010 Microchip Technology Inc.
DS70152H-page 59
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
8.0
AC/DC CHARACTERISTICS
AND TIMING REQUIREMENTS
Table 8-1 lists the AC/DC characteristics and timing
requirements.
TABLE 8-1:
AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
Standard Operating Conditions
Operating Temperature: –40C-85C. Programming at 25C is recommended.
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
D111
VDD
Supply Voltage During Programming
3.0
3.60
V
Normal programming(1)
D112 IPP
Programming Current on MCLR
—5
μA—
D113 IDDP
Supply Current During Programming
2
mA
D031 VIL
Input Low Voltage
VSS
0.2 VDD
V—
D041 VIH
Input High Voltage
0.8 VDD
VDD
V—
D080 VOL
Output Low Voltage
0.6
V
IOL = 8.5 mA @ 3.6V
D090 VOH
Output High Voltage
VDD – 0.7
V
IOH = -3.0 mA @ 3.6V
D012 CIO
Capacitive Loading on I/O pin (PGDx)
50
pF
To meet AC specifications
D013 CF
Filter Capacitor Value on VCAP
110
μF
Required for controller core
P1
TPGC
Serial Clock (PGCx) Period (ICSP)
200
ns
P1
TPGCL
Serial Clock (PGCx) Period (Enhanced
ICSP)
500
ns
P1A
TPGCL
Serial Clock (PGCx) Low Time (ICSP)
80
ns
P1A
TPGCL
Serial Clock (PGCx) Low Time (Enhanced
ICSP)
200
ns
P1B
TPGCH
Serial Clock (PGCx) High Time (ICSP)
80
ns
P1B
TPGCH
Serial Clock (PGCx) High Time (Enhanced
ICSP)
200
ns
P2
TSET1
Input Data Setup Time to Serial Clock
15
ns
P3
THLD1
Input Data Hold Time from PGCx
15
ns
P4
TDLY1
Delay between 4-bit Command and
Command Operand
40
ns
P4A
TDLY1A Delay between Command Operand and
Next 4-bit Command
40
ns
P5
TDLY2
Delay between Last PGCx
↓of Command
to First PGCx
↑ of Read of Data Word
20
ns
P6
TSET2VDD
↑ Setup Time to MCLR ↑
100
ns
P7
THLD2
Input Data Hold Time from MCLR
25
ms
P8
TDLY3
Delay between Last PGCx
↓of Command
Byte to PGDx
↑ by Programming
Executive
12
μs—
P9a
TDLY4
Programming Executive Command
Processing Time
10
μs—
Note 1: VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within
±0.3V of VDD and VSS, respectively.
2: Time depends on the FRC accuracy and the value of the FRC Oscillator tuning register. Refer to
“Electrical Characteristics” section in the specific device data sheet.
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