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2011-2012 Microchip Technology Inc.
Preliminary
DS61168D-page 5
PIC32MX1XX/2XX
Pin Diagrams (Continued)
28-Pin QFN(1,2,3)
= Pins are up to 5V tolerant
Note
1:
2:
Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more
information.
3:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
V
RE
F
-/
C
V
REF
-/
AN1/
RPA1
/CTED2/
R
A1
V
RE
F
+/CV
REF
+/A
N
0/C3
INC/R
P
A0/CTED1/RA0
MCLR
AV
DD
AV
SS
A
N
9/C3
INA/
RPB
15/
SCK2/
C
TED6/
P
MCS1
/RB1
5
CV
RE
F
/AN10
/C3INB/RPB14
/S
C
K1/CT
E
D5/P
MWR/RB
14
28
27
26
25
24
23
22
PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0
121
AN11/RPB13/CTPLS/PMRD/RB13
PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1
220
AN12/PMD0/RB12
AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
319
PGEC2/TMS/RPB11/PMD1/RB11
AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
4
PIC32MX110F016B
18
PGED2/RPB10/CTED11/PMD2/RB10
VSS
517
VCAP
OSC1/CLKI/RPA2/RA2
616
VSS
OSC2/CLKO/RPA3/PMA0/RA3
715
TDO/RPB9/SDA1/CTED4/PMD3/RB9
8
9
10
11
12
13
14
SO
S
C
I/R
PB
4
/R
B
4
S
O
SCO
/RP
A4/
T
1CK/
CTE
D
9/P
M
A1/
R
A4
V
DD
PGE
D
3/RP
B5/
P
MD7/
RB5
PGE
C
3/RP
B6/
P
MD6/
RB6
T
D
I/
RPB
7
/CTE
D3
/P
M
D
5
/I
N
T0
/RB
7
TCK
/RPB
8
/SCL1/CTED10/PMD4/RB8
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