參數(shù)資料
型號(hào)： PIC32MX250F128B-I/SP
廠商： Microchip Technology
文件頁(yè)數(shù)： 138/320頁(yè)
文件大?。?/td> 0K
描述： IC MCU 32BIT 128KB FLASH 28-SDIP
標(biāo)準(zhǔn)包裝： 15
系列： PIC® 32MX
核心處理器： MIPS32? M4K?
芯體尺寸： 32-位
速度： 40MHz
連通性： I²C，IrDA，LIN，PMP，SPI，UART/USART，USB OTG
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，DMA，I²S，POR，PWM，WDT
輸入/輸出數(shù)： 19
程序存儲(chǔ)器容量： 128KB（128K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 2.3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 9x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-DIP（0.300"，7.62mm）
包裝： 管件
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PIC32MX1XX/2XX
DS61168D-page 222
Preliminary
2011-2012 Microchip Technology Inc.
The processor will exit, or ‘wake-up’, from Sleep on one
of the following events:
On any interrupt from an enabled source that is
operating in Sleep. The interrupt priority must be
greater than the current CPU priority.
On any form of device Reset.
On a WDT time-out.
If the interrupt priority is lower than or equal to the
current priority, the CPU will remain Halted, but the
PBCLK will start running and the device will enter into
Idle mode.
25.3.2
IDLE MODE
In Idle mode, the CPU is Halted but the System Clock
(SYSCLK) source is still enabled. This allows peripher-
als to continue operation when the CPU is Halted.
Peripherals can be individually configured to Halt when
entering Idle by setting their respective SIDL bit.
Latency, when exiting Idle mode, is very low due to the
CPU oscillator source remaining active.
The device enters Idle mode when the SLPEN bit
(OSCCON<4>) is clear and a WAIT instruction is
executed.
The processor will wake or exit from Idle mode on the
following events:
On any interrupt event for which the interrupt
source is enabled. The priority of the interrupt
event must be greater than the current priority of
the CPU. If the priority of the interrupt event is
lower than or equal to current priority of the CPU,
the CPU will remain Halted and the device will
remain in Idle mode.
On any form of device Reset
On a WDT time-out interrupt
25.3.3
PERIPHERAL BUS SCALING
METHOD
Most of the peripherals on the device are clocked using
the PBCLK. The peripheral bus can be scaled relative to
the SYSCLK to minimize the dynamic power consumed
by the peripherals. The PBCLK divisor is controlled by
PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK to
PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals
using PBCLK are affected when the divisor is changed.
Peripherals such as the USB, Interrupt Controller, DMA,
and the bus matrix are clocked directly from SYSCLK.
As a result, they are not affected by PBCLK divisor
changes.
Changing the PBCLK divisor affects:
The CPU to peripheral access latency. The CPU
has to wait for next PBCLK edge for a read to
complete. In 1:8 mode, this results in a latency of
one to seven SYSCLKs.
The power consumption of the peripherals. Power
consumption is directly proportional to the fre-
quency at which the peripherals are clocked. The
greater the divisor, the lower the power consumed
by the peripherals.
To minimize dynamic power, the PB divisor should be
chosen to run the peripherals at the lowest frequency
that provides acceptable system performance. When
selecting a PBCLK divider, peripheral clock require-
ments, such as baud rate accuracy, should be taken
into account. For example, the UART peripheral may
not be able to achieve all baud rate values at some
PBCLK divider depending on the SYSCLK value.
Note 1: Changing the PBCLK divider ratio
requires recalculation of peripheral tim-
ing. For example, assume the UART is
configured for 9600 baud with a PB clock
ratio of 1:1 and a POSC of 8 MHz. When
the PB clock divisor of 1:2 is used, the
input frequency to the baud clock is cut in
half; therefore, the baud rate is reduced
to 1/2 its former value. Due to numeric
truncation in calculations (such as the
baud rate divisor), the actual baud rate
may be a tiny percentage different than
expected. For this reason, any timing cal-
culation required for a peripheral should
be performed with the new PB clock fre-
quency instead of scaling the previous
value based on a change in the PB divisor
ratio.
2: Oscillator start-up and PLL lock delays
are applied when switching to a clock
source that was disabled and that uses a
crystal and/or the PLL. For example,
assume the clock source is switched from
POSC to LPRC just prior to entering Sleep
in order to save power. No oscillator start-
up delay would be applied when exiting
Idle. However, when switching back to
POSC, the appropriate PLL and/or
oscillator start-up/lock delays would be
applied.
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PIC32MX250F128BT-50I/ML 制造商:Microchip Technology Inc 功能描述:32-BIT FAMILY, 128KB FLASH, 32 KB RAM, 50MHZ - Tape and Reel 制造商:Microchip Technology Inc 功能描述:IC MCU 32BIT 128KB FLASH 28QFN 制造商:Microchip Technology Inc 功能描述:32-bit family, 128KB FLASH, 32 KB RAM, 50MHz, 28 QFN 6x6x0.9mm T/R
PIC32MX250F128BT-50I/SO 制造商:Microchip Technology Inc 功能描述:32-BIT FAMILY, 128KB FLASH, 32 KB RAM, 50MHZ - Tape and Reel 制造商:Microchip Technology Inc 功能描述:IC MCU 32BIT 128KB FLASH 28SOIC 制造商:Microchip Technology Inc 功能描述:32-bit family, 128KB FLASH, 32 KB RAM, 50MHz, 28 SOIC .300in T/R
PIC32MX250F128BT-50I/SS 制造商:Microchip Technology Inc 功能描述:32-BIT FAMILY, 128KB FLASH, 32 KB RAM, 50MHZ - Tape and Reel 制造商:Microchip Technology Inc 功能描述:IC MCU 32BIT 128KB FLASH 28SSOP 制造商:Microchip Technology Inc 功能描述:32-bit family, 128KB FLASH, 32 KB RAM, 50MHz, 28 SSOP .209in T/R
PIC32MX250F128BT-I/ML 功能描述:32位微控制器 - MCU 32B 128KB FL 32KB RAM 40MHz 28 Pin RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT
PIC32MX250F128BT-I/SO 功能描述:32位微控制器 - MCU 32B 128KB FL 32KB RAM 40MHz 28 Pin RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT
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