參數(shù)資料
型號: PIC32MX360F512LT-80I/BG
廠商: Microchip Technology
文件頁數(shù): 9/44頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 512KB FLASH 121XBGA
標準包裝: 2,200
系列: PIC® 32MX
核心處理器: MIPS32? M4K?
芯體尺寸: 32-位
速度: 80MHz
連通性: I²C,IrDA,LIN,PMP,SPI,UART/USART
外圍設備: 欠壓檢測/復位,DMA,POR,PWM,WDT
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 121-TFBGA
包裝: 帶卷 (TR)
PIC32 Architecture
2008 Microchip Technology Inc.
DS61146B-page 13
Communication channels:
USB 2.0 compliant (FS. 12 Mbps), OTG, Host and Device-only capable
2 enhanced UART channels with hardware IrDA
2 Master/Slave/Frame mode SPI channels
2 Master/Slave I2C channels, 10/7 bits mode addressing, broadcast capable
Analog-to-Digital Converters:
Up to 16 Channels, each 10-bit resolution ADCs
Up to 500+ kilo-samples per second (ksps) conversion speed
Software selectable Internal or External voltage reference
Automatic Channel Scan mode
Selectable conversion trigger source
16 word conversion result buffer
Selectable Buffer Fill modes
Eight result alignment options
Operation during CPU Sleep mode
Timers:
5 16-bit timer/counter with the ability to form up to (2) 32-bit timer/counters
Software-selectable internal or external clock source
Asynchronous timer/counter with built-in oscillator
Programmable interrupt generation and priority
Gated external pulse counter
Software-selectable prescalers.
Operational during CPU Sleep mode
Core Timer:
32 bit timer in CPU for implementing a timer interrupt function.
RTCC (Real-Time Clock and Calendar):
Time with hours, minutes and seconds
Calendar with weekday, date, month and year
Leap year detection
Highly configurable alarm
Calibration of up to 260 ppm of crystal error
Debug and Programming:
6 instructions and 2 data breakpoints
2 complex breakpoint logic blocks with qualified/primed breakpoint triggers, Pass
counters, and stopwatch timers.
4-wire EJTAG and 2-wire Microchip interface
2-wire Microchip Interface:
- 6 real-time read/write capture logic blocks
- Read/write access to all data RAM and SFRs without stopping CPU
Instruction Trace Port:
- 5-Wire, nonintrusive trace port
- Triggered by complex breakpoint logic block
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