參數(shù)資料
型號(hào): PIC32MX675F256LT-80I/PF
廠商: Microchip Technology
文件頁數(shù): 22/64頁
文件大?。?/td> 0K
描述: MCU 32BIT 256K FLASH 100TQFP
標(biāo)準(zhǔn)包裝: 1,000
系列: PIC® 32MX
核心處理器: MIPS32? M4K?
芯體尺寸: 32-位
速度: 80MHz
連通性: 以太網(wǎng),I²C,SPI,UART/USART,USB OTG
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 85
程序存儲(chǔ)器容量: 256KB(256K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
包裝: 帶卷 (TR)
2007-2012 Microchip Technology Inc.
DS61145K-page 29
PIC32MX
14.0
VERIFY DEVICE MEMORY
The verify step involves reading back the code memory
space and comparing it against the copy held in the
programmer’s buffer. The Configuration registers are
verified with the rest of the code.
14.1
Verifying Memory with the PE
Memory verify is performed using the GET_CRC
command, as shown in Table 16-2.
FIGURE 14-1:
VERIFYING MEMORY
WITH THE PE
The following steps are required to verify memory using
the PE:
1.
XferFastData (GET_CRC).
2.
XferFastData (start_Address).
3.
XferFastData (length).
4.
valCkSum = XferFastData (32’h0x00).
Verify that valCkSum matches the checksum of the
copy held in the programmer’s buffer.
14.2
Verifying Memory without the PE
Reading from Flash memory is performed by executing
a series of read accesses from the Fastdata register.
Table 19-4 shows the EJTAG programming details,
including the address and op code data for performing
processor access operations.
FIGURE 14-2:
VERIFYING MEMORY
WITHOUT THE PE
The following steps are required to verify memory:
1.
XferInstruction
(op code).
2.
Repeat Step 1 until the last instruction is
transferred to the CPU.
3.
Verify that valRead matches the copy held in the
programmer’s buffer.
4.
Repeat Steps 1-3 for each memory location.
TABLE 14-1:
VERIFY DEVICE OP CODES
Note:
Because
the
Configuration
registers
include the device code protection bit,
code memory should be verified immedi-
ately after writing (if code protection is
enabled). This is because the device will
not be readable or verifiable if a device
Reset occurs after the code-protect bit
has been cleared.
Issue Verify Command
Receive Response
Op code
Instruction
Step 1: Initialize some constants.
3c13ff20
lui $s3, 0xFF20
Step 2: Read memory Location.
3c08<ADDR>
3508<ADDR>
lui $t0,<FLASH_WORD_ADDR(31:16)>
ori $t0,<FLASH_WORD_ADDR(15:0)>
Step 3: Write to Fastdata location.
8d090000
ae690000
lw $t1, 0($t0)
sw $t1, 0($s3)
Step 4: Read data from Fastdata register
0xFF200000.
Step 5: Repeat Steps 2-4 until all configuration
locations are read.
Read Memory Location
Verify Location
Done
No
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