參數(shù)資料
型號(hào): PIC32MX675F256LT-80I/PT
廠商: Microchip Technology
文件頁(yè)數(shù): 37/64頁(yè)
文件大?。?/td> 0K
描述: MCU 32BIT 256K FLASH 100TQFP
標(biāo)準(zhǔn)包裝: 1,200
系列: PIC® 32MX
核心處理器: MIPS32? M4K?
芯體尺寸: 32-位
速度: 80MHz
連通性: 以太網(wǎng),I²C,SPI,UART/USART,USB OTG
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 85
程序存儲(chǔ)器容量: 256KB(256K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
包裝: 帶卷 (TR)
PIC32MX
DS61145K-page 42
2007-2012 Microchip Technology Inc.
17.0
CHECKSUM
17.1
Theory
The checksum is calculated as the 32-bit summation of
all bytes (8-bit quantities) in program Flash, boot Flash
(except device Configuration Words), the Device ID
register with applicable mask, and the device Configu-
ration Words with applicable masks. Next, the 2’s
complement of the summation is calculated. This final
32-bit number is presented as the checksum.
17.2
Mask Values
The mask value of a device Configuration is calculated
by setting all the unimplemented bits to ‘0’ and all the
implemented bits to ‘1’.
For example, Register 17-1 shows the DEVCFG0 reg-
ister of the PIC32MX360F512L device. The mask value
for this register is:
mask_value_devcfg0
= 0x110FF00B
Table 17-1 lists the mask values of the four device Con-
figuration registers and Device ID registers to be used
in the checksum calculations.
REGISTER 17-1:
DEVCFG0 REGISTER OF PIC32MX360F512L
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
r-0
r-1
R/P-1
r-1
R/P-1
—CP
—BWP
23:16
r-1
R/P-1
PWP19
PWP18
PWP17
PWP16
15:8
R/P-1
r-1
PWP15
PWP14
PWP13
PWP12
7:0
r-1
R/P-1
r-1
R/P-1
ICESEL
DEBUG<1:0>
Legend:
P = Programmable bit
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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