參數(shù)資料
型號(hào): PIC32MX775F512H-80I/PT
廠商: Microchip Technology
文件頁(yè)數(shù): 13/64頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32BIT 512K FLASH 64TQFP
特色產(chǎn)品: 32-Bit PIC? Microcontroller
PIC32 32-Bit MCU Families
標(biāo)準(zhǔn)包裝: 160
系列: PIC® 32MX
核心處理器: MIPS32? M4K?
芯體尺寸: 32-位
速度: 80MHz
連通性: CAN,以太網(wǎng),I²C,SPI,UART/USART,USB OTG
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 53
程序存儲(chǔ)器容量: 512KB(512K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 650 (CN2011-ZH PDF)
PIC32MX
DS61145K-page 20
2007-2012 Microchip Technology Inc.
7.0
ENTERING 2-WIRE ENHANCED
ICSP MODE
To use the 2-wire PGEDx and PGECx pins for pro-
gramming, they must be enabled. Note that any pair of
programming pins available on a particular device may
be used, however, they must be used as a pair. PGED1
must be used with PGEC1, and so on.
The following steps are required to enter 2-wire
Enhanced ICSP mode:
1.
The MCLR pin is briefly driven high, then low.
2.
A 32-bit key sequence is clocked into PGEDx.
3.
MCLR is then driven high within a specified
period of time and held.
and Timing Requirements” for timing requirements.
The programming voltage applied to MCLR is VIH,
which is essentially VDD, in PIC32MX devices. There is
no minimum time requirement for holding at VIH. After
VIH is removed, an interval of at least P18 must elapse
before presenting the key sequence on PGEDx.
The key sequence is a specific 32-bit pattern: ‘0100
1101
0100
0011
0100
1000
0101
0000
’ (the
acronym ‘MCHP’, in ASCII). The device will enter
Program/Verify mode only if the key sequence is valid.
The MSb of the Most Significant nibble must be shifted
in first.
Once the key sequence is complete, VIH must be
applied to MCLR and held at that level for as long as
the 2-wire Enhanced ICSP interface is to be main-
tained. An interval of at least time P19 and P7 must
elapse before presenting data on PGEDx. Signals
appearing on PGEDx before P7 has elapsed will not be
interpreted as valid.
Upon successful entry, the programming operations
documented in subsequent sections can be performed.
While in 2-wire Enhanced ICSP mode, all unused I/Os
are placed in the high-impedance state.
FIGURE 7-1:
ENTERING ENHANCED ICSP MODE
Note:
If using the 4-wire JTAG interface, the
following procedure is not necessary.
MCLR
PGEDx
PGECx
VDD
P6
P14
b31
b30
b29
b28
b27
b2
b1
b0
b3
...
Program/Verify Entry Code = 0x4D434850
P1A
P1B
P18
P19
01
0
1
0
P7
VIH
P20
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