參數(shù)資料
型號(hào): PIC7100
英文描述: Peripheral IC
中文描述: 外圍芯片
文件頁數(shù): 1/4頁
文件大?。?/td> 211K
代理商: PIC7100
1
PXXXX 06/01/00
Product Features
All three ports compliant with the
PCI Local Bus
Specification, Revision 2.1
Compliant with
PCI-to-PCI Bridge Architecture Specification,
Revision 1.0
32-Bit Primary and two Secondary Ports
Circular-Delta Bus Architecture
Concurrent primary to secondary bus operation and indepen-
dent intra-secondary port channel to reduce traffic on the
primary port
Provides arbitration for two sets of 8 secondary bus masters
Programmable 2-level priority arbiters
Disable control for use of external arbiter
Support PCI transactions for:
All I/O and memory commands
Type 1 to Type 0 configuration conversion
(downstream only)
Type 1 to Type 1 configuration forwarding
Type 1 to special cycle configuration conversion
Supports posted memory write buffers in all directions
Implements delayed transactions for all PCI configuration,
I/O and memory read commands
Supports positive medium decoding
Enhanced address decoding
32-Bit I/O address range
32-Bit memory-mapped I/O address range
VGA addressing and VGA palette snooping
ISA-aware mode for legacy support in the first 64KB of
I/O address range
IEEE 1149.1 JTAG interface support
Full scan support
3.3V core logic with 5V tolerant 3.3V PCI signaling interface
256-pin plastic PBGA package (NA256)
Supports system transaction ordering rules
Hot-Plug "Ready"
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PI7C7100
Datasheet Brief
Product Description
Pericoms PI7C7100 is the first triple port PCI-to-PCI Bridge
device designed to be fully compliant with the 32-Bit, 33 MHz
implementation of the PCI Local Bus Specification, Revision 2.1.
The PI7C7100 supports synchronous bus transactions between
devices on the primary bus and the secondary buses both
operating at 33 MHz. The primary and the secondary buses can
also operate in concurrent mode, resulting in additional increase
in system performance. Concurrent bus operation offloads and
isolates unnecessary traffic from the primary bus; thereby
enabling a master and a target device on the same secondary PCI
bus to communicate even while the primary bus is busy.
Product Benefits
Triple port PCI-to-PCI Bridge increases the number of PCI slots
that can be supported in a system.
Single PI7C7100 device instead of two PCI-to-PCI Bridge
devices conserves board real estate and provides one less
device load on the primary bus.
Concurrent and intra-secondary bus communication increases
overall system performance by reducing bus traffic on the
primary bus. Devices on secondary busses can independently
communicate while the primary bus is busy.
Integrated two-level programmable arbiter support for up to 8
devices on each secondary bus maximizes master device
control. The internal arbiter can be bypassed with an external
arbiter for custom applications.
Synchronous clock operation on the primary and secondary
busses
Enhanced PCI bridge performance and efficiency through
support for delayed transactions.
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