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參數(shù)資料
型號(hào): PK20N512VLL100
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 25/74頁(yè)
文件大?。?/td> 0K
描述: IC ARM CORTEX MCU 512K 100-LQFP
產(chǎn)品培訓(xùn)模塊: Kinetis® Cortex-M4 Microcontroller Family
標(biāo)準(zhǔn)包裝: 1
系列: Kinetis
核心處理器: ARM? Cortex?-M4
芯體尺寸: 32-位
速度: 100MHz
連通性: CAN,EBI/EMI,I²C,IrDA,SDHC,SPI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,I²S,LVD,POR,PWM,WDT
輸入/輸出數(shù): 66
程序存儲(chǔ)器容量: 512KB(512K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 25x16b,D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 100-LQFP
包裝: 托盤
Table 16. Oscillator DC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Vpp5
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
VDD
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
0.6
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
V
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.3.2.2 Oscillator frequency specifications
Table 17. Oscillator frequency specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fosc_lo
Oscillator crystal or resonator frequency — low
frequency mode (MCG_C2[RANGE]=00)
32
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — high
frequency mode (low range)
(MCG_C2[RANGE]=01)
3
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
32
MHz
fec_extal
Input clock frequency (external clock mode)
50
MHz
1, 2
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
tcst
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
3, 4
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
250
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
0.6
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
1
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it
remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
31
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