參數(shù)資料
型號(hào): PK60N512VLQ100
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 33/79頁(yè)
文件大小: 0K
描述: IC ARM CORTEX MCU 512K 144-LQFP
產(chǎn)品培訓(xùn)模塊: Kinetis® Cortex-M4 Microcontroller Family
標(biāo)準(zhǔn)包裝: 1
系列: Kinetis
核心處理器: ARM? Cortex?-M4
芯體尺寸: 32-位
速度: 100MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,IrDA,SDHC,SPI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,I²S,LVD,POR,PWM,WDT
輸入/輸出數(shù): 100
程序存儲(chǔ)器容量: 512KB(512K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 33x16b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 144-LQFP
包裝: 托盤(pán)
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 25. Flexbus limited voltage range switching specifications
Num
Description
Min.
Max.
Unit
Notes
Operating voltage
2.7
3.6
V
Frequency of operation
FB_CLK
MHz
FB1
Clock period
20
ns
FB2
Address, data, and control output valid
11.5
ns
FB3
Address, data, and control output hold
0.5
ns
FB4
Data and FB_TA input setup
8.5
ns
FB5
Data and FB_TA input hold
0.5
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 26. Flexbus full voltage range switching specifications
Num
Description
Min.
Max.
Unit
Notes
Operating voltage
1.71
3.6
V
Frequency of operation
FB_CLK
MHz
FB1
Clock period
1/FB_CLK
ns
FB2
Address, data, and control output valid
13.5
ns
FB3
Address, data, and control output hold
0
ns
FB4
Data and FB_TA input setup
13.7
ns
FB5
Data and FB_TA input hold
0.5
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Peripheral operating requirements and behaviors
K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
39
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