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參數(shù)資料
| 型號(hào)： | PKD01BIEY |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CDIP14 |
| 封裝： | CERDIP-14 |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 402K |
| 代理商： | PKD01BIEY |
REV. A
PKD01
–15–
20k
1%
INPUT
(GAIN = –2)
DET/RST
PKD01
D1
CH
1000pF
C
A
B
8.2k
5%
30.1k
1%
10k
1%
10k
1%
RESET
VOLTAGE = –1V
(RESETS TO –4V)
7.5k
5%
RST
V+
V–
OUTPUT
A GAIN = –2
B GAIN = +4
+2V
0V
–5V
+10V
0V
–4V
–10V
INPUT
OUTPUT
TIME – 50 s/DIV
Figure 15. Negative Peak Detector with Gain
10k
1%
VIN
DET
PKD01
D1
CH
1000pF
C
A
B
10k
5%
10k
1%
RESET
VOLTAGE
V+
V–
OUTPUT
A GAIN = –1
B GAIN = +1
0V
+10V
0V
–10V
INPUT
OUTPUT
TIME – 50 s/DIV
Figure 16. Unity Gain Negative Peak Detector
PKD01
CH
1000pF
C
A
B
RESET
VOLTAGE
OUTPUT
INPUT AMPLIFIER GAIN
RESET AMPLIFIER GAIN
= 1 +
R3 = R4 =
1
+
R2
R4
INPUT
R1
1
R1
1
R2
R1
R3
IF BOTH INPUT SIGNAL (AMPLIFIER A INPUT) AND THE RESET
VOLTAGE (AMPLIFIER B INPUT) HAVE THE SAME POSITIVE
VOLTAGE GAIN,THE GAIN CAN BE SET BY A SINGLE VOLTAGE
DIVIDER FOR BOTH INPUT AMPLIFIERS.
NOTE:
R1, R2, R3 AND R4 > 5k
Figure 17. Alternate Gain Configuration
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PKD01BY | 制造商:Analog Devices 功能描述: |
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| PKD01EPZ | 制造商:Analog Devices 功能描述:Sample and Hold 2-CH 70us 14-Pin PDIP 制造商:Analog Devices 功能描述:Sample & Hold Amplifier |
| PKD01EY | 制造商:Analog Devices 功能描述: |
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