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參數資料
| 型號： | PKF4610ASI |
| 廠商： | POWER-ONE INC |
| 元件分類： | 電源模塊 |
| 英文描述： | 1-OUTPUT 6.6 W DC-DC REG PWR SUPPLY MODULE |
| 封裝： | SMT-18 |
| 文件頁數： | 5/16頁 |
| 文件大?。?/td> | 1528K |
| 代理商： | PKF4610ASI |
13
EN/LZT 146 30 R2A Ericsson Microelectronics AB, October 2000
Voltage Margining
For voltage controlled margining e.g. at final test, the following
setup can be used. By increasing the control voltage V1 to +10 V the
output voltage decreases 5% of VOi, and by decreasing V1 to –10 V
the output voltage increases 5%.
Capacitive Load
The PKF series has no maximum limit for capacitive load on the out-
put. The power module may operate in current limiting mode during
start-up, affecting the ramp-up and the start-up time. For optimum
start performance we recommend maximum 100
mF/A of IO. Connect
capacitors at the point of load for best performance.
Input and Output Impedance
Both the source impedance of the power feeding and the load imped-
ance will interact with the impedance of the DC/DC power module.
It is most important to have the ratio between L and C as low as
possible, i.e. a low characteristic impedance, both at the input and
output, as the power modules have a low energy storage capability.
Use an electrolytic capacitor across the input if the source inductance
is higher than 10
mH. Their equivalent series resistance together
with the capacitance acts as a lossless damping filter. Suitable capaci-
tor values are in the range 10–100
mF.
Parallel Operation
Paralleling of several converters is easily accomplished by direct
connection of the output voltage terminal pins. The load regulation
characteristic is specifically designed for optimum paralleling per-
formance. Load sharing between converters will be within ±10%. It
is recommended not to exceed PO = n × 0.9 × POmax, where POmax is
the maximum converter output power and n the number of paralleled
converters, to prevent overloading any of the converters and thereby
decreasing the reliability performance.
Precision load regulation for the PKF 4000A series
PKF 4000A I has a load regulation which allows paralleling of the
power modules without external control. If there is a need for tighter
voltage regulation, the figure below (fig. 7) shows how to obtain a
very exact voltage.
The output voltage is divided by two resistors and compared with a
reference voltage. Out 1 integrates the voltage difference and the
signal is fed back to output adjust by an opto coupler. Please note:
The operational amplifier must be a single supply in order to operate
at the actual output voltage if there are no other voltages available.
The opto coupler should have a current gain of 25–200%.
The output voltage is: Uout = Uref × (R2 + R1)/R2
Other output voltages and reference voltages may be used. R1 and
R2 is calculated from formula above. Please keep the values in the
same range as in table below.
Table for selecting resistor values depending on desired output
voltage.
1.8 V
2.5V
3.3V
R1(
W)
160 k
200 k
220 k
R2(
W)
330 k
191 k
130 k
R3(
W)
21 k
6.8 k
1 k
Synchronization (Sync)
It is possible to synchronize the switching frequency to an external
symmetrical clock signal. The input can be driven by an TTL-com-
patible output and referenced to the input pin 17.
Characteristics
min
typ
max
unit
High level
2.2
6.5
V
Threshold level*)
1.2
1.7
2.2
V
Low level
0
0.4
V
Sink current
1.5
mA
Sync. frequency
520
688
kHz
*)
Rise time <10ns
Current Limiting Protection (Ilim)
The output power is limited at loads above the output current
limiting threshold (Ilim), specified as a minimum value.
Figure 6
Figure 7
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