參數(shù)資料
型號: PL-2303
廠商: Electronic Theatre Controls, Inc.
元件分類: RS-232
英文描述: 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors
中文描述: 5V的高速RS - 232收發(fā)器與0.1uF電容
文件頁數(shù): 5/11頁
文件大?。?/td> 144K
代理商: PL-2303
Release Date:
J uly, 2002
ds_pl2303_v14
Overview
PL-2303 Product Datasheet
-
5 -
Document Revision 1.3
The PL-2303 operates as a bridge between one USB port and one standard RS232 Serial port. The two
large on-chip buffers accommodate data flow from two different buses. The USB bulk-type data is adopted
for maximum data transfer. Automatic handshake is supported at the Serial port. With these, a much higher
baud rate can be achieved compared to the legacy UART controller.
This device is also compliant with USB power management and remote wakeup scheme. Only minimum
power is consumed from the host during Suspend. By integrating all the function in a SOIC-28 package, this
chip is suitable for cable embedding. Users just simply hook the cable into PC or hub’s USB port, and then
they can connect to any RS-232 devices.
Pin Description
Table 1. Pins Description
Pin
No.
1
2
3
4
Name
Type
Description
TXD
DTR_N
RTS_N
VDD_232
O
O
O
P
Data output to Serial port
Data Terminal Ready, active low
Request To Send, active low
RS-232 VDD. The RS-232 output signals (Pin 1 ~ Pin 3) are
designed for 5V, 3.3V or 3V operation. VDD_232 should be
connected to the same power level of the RS-232 interface.
(The RS-232 input signals are always 5V~3V tolerant.)
Note: This document version only provides 5V DC characteristic
information. Refer to future revisions for updates.
Data input from Serial Bus
Ring Indicator, active low
Ground
Power
Data Set Ready, active low
Data Carrier Detect, active low
Clear To Send, active low
Shut Down RS232 Transceiver
During Reset, this pin is input for simulation purpose. During
normal operation, this pin is Serial ROM clock
Serial ROM data signal
USB DPLUS signal
USB DMINUS signal
3.3V power for USB transceiver
3.3V ground
System Reset
Power
Ground
5
6
7
8
9
10
11
12
13
RXD
RI_N
GND
VDD
DSR_N
DCD_N
CTS_N
SHTD_N
EE_CLK
I
I
P
P
I
I
I
O
I/O
14
15
16
17
18
19
20
21
EE_DATA
DP
DM
VDD_3V3
GND_3V3
RESET
VDD
GND
I/O
I/O
I/O
P
P
I
P
P
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