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參數(shù)資料
| 型號： | PLC18V8ZIAA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | Zero standby power CMOS versatile PAL devices |
| 中文描述： | OT PLD, 25 ns, PQCC20 |
| 封裝： | PLASTIC, MO-047AA, SOT-380-1, LCC-20 |
| 文件頁數(shù)： | 5/23頁 |
| 文件大?。?/td> | 225K |
| 代理商： | PLC18V8ZIAA |
Philips Semiconductors
Product specification
PLC18V8Z
Zero standby power
CMOS versatile PAL devices
1997 Aug 08
5
LOGIC DIAGRAM
Pins 1 and 11 are configured as Inputs 0 and 9, respectively, via the configuration cell. The clock and OE
functions are disabled.
All output macro cells (OMC) are configured as bidirectional I/O, with the outputs disabled via the direc-
tion term.
Denotes a programmable cell location.
1
2
3
4
5
6
7
8
9
NOTES:
In the unprogrammed or virgin state:
All cells are in a conductive state.
All AND gate locations are pulled to a logic “0” (Low).
Output polarity is inverting.
0
4
8
12
16
20
24
28
32
35
SP
AR
CLK
OE
AC1
AC2
DIR
CLK
F7
19
11
SP
AR
CLK
OE
AC1
AC2
DIR
F6
18
SP
AR
CLK
OE
AC1
AC2
DIR
F5
17
SP
AR
CLK
OE
AC1
AC2
DIR
F4
16
SP
AR
CLK
OE
AC1
AC2
DIR
F3
15
SP
AR
CLK
OE
AC1
AC2
DIR
F2
14
SP
AR
CLK
OE
AC1
AC2
DIR
F1
13
SP
AR
CLK
OE
AC1
AC2
DIR
F0
12
SP
AR
I9/OE
I0/CLK
I1
I2
I3
I4
I5
I6
I7
I8
I
0
I
0
I
9
I
9
I
8
I
8
F
0
F
0
I
7
I
7
F
1
F
1
I
6
I
6
F
2
F
2
I
5
I
5
F
3
F
3
I
4
I
4
F
4
F
4
I
3
I
3
F
5
F
5
I
2
I
2
F
6
F
6
I
1
I
1
F
7
F
7
CONFIG.
CELL
SP00012
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