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參數(shù)資料
| 型號(hào)： | PLC18V8ZIADB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | Zero standby power CMOS versatile PAL devices |
| 中文描述： | OT PLD, 25 ns, PDSO20 |
| 封裝： | 5.30 MM, PLASTIC, MO-150AE, SOT-339-1, SSOP-20 |
| 文件頁數(shù)： | 12/23頁 |
| 文件大小： | 225K |
| 代理商： | PLC18V8ZIADB |
Philips Semiconductors
Product specification
PLC18V8Z
Zero standby power
CMOS versatile PAL devices
1997 Aug 08
12
POWER-UP RESET
In order to facilitate state machine design and testing, a power-up
reset function has been incorporated in the PLC18V8Z. All internal
registers will reset to Active-Low (logical “0”) after a specified period
of time (t
PPR
). Therefore, any OMC that has been configured as a
registered output will always produce an Active-High on the
associated output pin because of the inverted output buffer. The
internal feedback (Q) of a registered OMC will also be set Low. The
programmed polarity of OMC will not affect the Active-High output
condition during a system power-up condition.
TIMING DIAGRAMS
éééé
éééééééé
éééééééé
éééééééé
éééééééé
éééééééé
ééééééééééééééééééééé
ééééééééééééééééééééé
t
PD
ééé
ééé
éééééééé
éééééééé
Switching Waveforms
VALID INPUT
VALID INPUT
3–STATE
3-STATE
INPUTS
I/O, REG.
FEEDBACK
CLK
PIN 11 OE
REGISTERED
OUTPUTS
ANY INPUT
PROGRAMMED FOR
DIRECTION CONTROL
COMBINATORIAL
OUTPUTS
t
IS
t
IH
t
CKH
t
CKL
t
CKP
t
CKO
t
OD1
t
OD2
t
OE2
t
OE1
Power-Up Reset
NOTE:
Diagram presupposes that the outputs (F) are enabled. The reset occurs regardless of the output condition (enabled or disabled).
t
CKP
t
CKH
t
CKL
t
IS
1.5V
1.5V
1.5V
t
CKL
t
IH
t
IS
1.5V
1.5V
t
CKO
1.5V
t
PPR
4.5V
3.0V
+5V
0V
V
OH
V
OL
+3V
0V
+3V
0V
V
CC
F
(OUTPUTS)
I, B
(INPUTS)
CLK
SP00020
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