Rev. F 08/09
5
PLC810PG
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Figure 3.
Block Diagram of PLC810PG. Reserved Pins are not Shown.
Block Diagram
Figure 3 shows a block diagram of the functional elements that
make up the PLC810PG. The reserved pins are not shown in
the diagram. Those pins are reserved for PI use during
manufacture and testing. The PLC810PG PFC control blocks
and circuits are shown on the upper half of the block diagram,
while the LLC control blocks are shown on the lower half. Some
of the functional blocks are shared.
PLC810PG Power Block
The PLC810PG is powered through VCC and VCCL pins. The
VCCL pin powers the LLC driver while VCC powers the rest of the
device. VCC pin must be supplied by a voltage between V
UVLO(+)
and 15 V. The provided supply is continuously compared against
the V
UVLO(+) and VUVLO(-) thresholds to start/stop the PLC810PG.
When VCC is above the V
UVLO(+) threshold the PLC810PG de-
asserts the undervoltage lockout (UVLO) signal allowing the device
to start. If VCC falls below V
UVLO(-), the UVLO signal is asserted,
shutting down the PLC810PG.
The VCCL pin powers the LLC driver, and VCCHB provides the
charge for the LLC high-side MOSFET for gate drive.
An internal linear regulator is used to generate a 3.3 V rail to power
the low voltage circuits inside the PLC810PG. The 3.3 V is brought
outside on the VREF pin allowing external low voltage circuits to be
powered by the PLC810PG.
PI-5041-112608
+
-
+
-
+
-
+
-
+
-
+
-
+
-
(6) GATEP
(7) VCC
(4) VREF
(13) VCCHB
(12) GATEH
(14) HB
(16) VCCL
(9) GNDL
VOC
VOVH
OTA
VIN(H)/VIN(L)
VSD(H)VSD(L)
LLC OFF
OVL FAULT
LLC OFF
LLC FAULT
VISL(F)VISL(S)
SOFT
START
CLAMP
OVL FAULT
OV FAULT
VFBPREF
PFC INHIBIT
OC FAULT
LLC CLOCK
VREF
PFC
F
AUL
T
VUVLO(+)
VUVLO(-)
ISP (3)
VCOMP (1)
FBP (23)
GND (2,19)
ISL (22)
(8) GNDP
(10) GATEL
DVGA
and LPF
PWM
RESET
INTERNAL REFERENCE
GENERATOR
INVERSION
3.3 V LINEAR
REGULATOR
ONE SHOT
4096
CYCLES
+
-
CLAMP
1.2 V
FBL (20)
FMAX (21)
LLC CURRENT
FEEDBACK
RAMP AND CLOCK
GENERATOR
DEAD TIME
GENERATOR
NON-
OVERLAP
GENERATOR
PHASE
ALIGNMENT
UVLO