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參數(shù)資料
| 型號： | PLDC20G10-35JC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | CMOS Generic 24-Pin Reprogrammable Logic Device |
| 中文描述： | OT PLD, 35 ns, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 393K |
| 代理商： | PLDC20G10-35JC |
USE ULTRA37000 FOR
ALL NEW DESIGNS
PLDC20G10B
PLDC20G10
Document #: 38-03010 Rev. *A
Page 6 of 14
AC Test Loads and Waveforms (Commercial)
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
OUTPUT
50pF
2.08V=V
thc
OUTPUT
2.13V=V
thm
(a)
(b)
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
5 pF
R1 238
(319
MIL)
R1 238
(319
MIL)
R2 170
(236
MIL)
R2 170
(236
MIL)
Equivalent to: THéVENIN EQUIVALENT (Commercial)
99
Equivalent to: THéVENIN EQUIVALENT (Military/Industrial)
136
Switching Characteristics
Over Operating Range
[3, 8, 9]
Parameter
t
PD
t
EA
t
ER
t
PZX
t
PXZ
t
CO
t
S
t
H
t
P[10]
t
WH
t
WL
f
MAX[11]
Description
Commercial
B–20
Min.
Max.
20
20
20
15
15
12
12
0
24
10
10
41.6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
B–15
–25
–35
Min.
Max.
15
15
15
12
12
10
Min.
Max.
25
25
25
20
20
15
Min.
Max.
35
35
35
25
25
25
Input or Feedback to Non-Registered Output
Input to Output Enable
Input to Output Disable
Pin 11 to Output Enable
Pin 11 to Output Disable
Clock to Output
Input or Feedback Set-up Time
Hold Time
Clock Period
Clock High Time
Clock Low Time
Maximum Frequency
12
0
22
8
8
45.4
15
0
30
12
12
33.3
30
0
55
17
17
18.1
Switching Characteristics
Over Operating Range
[3, 8, 9]
Parameter
t
PD
t
EA
t
ER
t
PZX
t
PXZ
t
CO
t
S
t
H
Notes:
8. Part (a) of AC Test Loads and Waveforms used for all parameters except t
, t
, and t
. Part (b) of AC Test Loads and Waveforms used for t
, t
, and t
.
9. The parameters t
and t
are measured as the delay from the input disable logic threshold transition to V
OH
– 0.5V for an enabled HIGH output or V
OL
+
0.5V for an enabled LOW input.
10.t
, minimum guaranteed clock period is that guaranteed for state machine operation and is calculated from t
P
= t
S
+ t
CO
. The minimum guaranteed period for
registered data path operation (no feedback) can be calculated as the greater of (t
+ t
) or (t
+ t
).
11. f
, minimum guaranteed operating frequency, is that guaranteed for state machine operation and is calculated from f
MAX
= 1/(t
S
+ t
CO
). The minimum
guaranteed f
MAX
for registered data path operation (no feedback) can be calculated as the lower of 1/(t
WH
+ t
WL
) or 1/(t
S
H
).
Description
Military/Industrial
B–25
Min.
Max.
25
25
25
20
20
15
18
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
B–20
–30
–40
Min.
Max.
20
20
20
17
17
15
Min.
Max.
30
30
30
25
25
20
Min.
Max.
40
40
40
25
25
25
Input or Feedback to Non-Registered Output
Input to Output Enable
Input to Output Disable
Pin 11 to Output Enable
Pin 11 to Output Disable
Clock to Output
Input or Feedback Set-Up Time
Hold Time
15
0
20
0
35
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PLDC20G10-35JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP PLD |
| PLDC20G10-35PC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CMOS Generic 24-Pin Reprogrammable Logic Device |
| PLDC20G10-35PI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP PLD |
| PLDC20G10-35WC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP PLD |
| PLDC20G10-35WI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP PLD |
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