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參數(shù)資料
| 型號： | PLLCORE60 |
| 英文描述： | 12-Bit Rail-to-Rail Micropower DACs in SO-8; Package: PDIP; No of Pins: 8; Temperature Range: 0°C to +70°C |
| 中文描述： | 鎖相環(huán) |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 26K |
| 代理商： | PLLCORE60 |
AMERICAN MICROSYSTEMS, INC
AMI5LG Gate Array
AMI5LS Standard Cell
PLLCORExxx
November 1998
AMI5LG & AMI5LS CMOS
Page 2 of 4
Logic Symbol
PLLCORExxx
refclk
sysclk
lf<3:0>
pd
rn
tstvcopad
vcoclk
tstcppad
Pin Description
Signal
Signal Description
LF<3:0>
Control inputs to program loop filter
PD
Power down input from core to place PLL in low power mode (asserted high)
REFCLK
Reference clock from core supplied by chip pad cell or core logic
RN
Reset signal from core to reset PLL and discharge loop filter (asserted low)
SYSCLK
System clock to core (when TSTE = 1, SYSCLK = TSTCLK)
VCOCLK
VCO output to divider logic or to PLL test logic this signal should not be used for a core clock
TSTCPPAD
External test pin: output from charge pump
TSTVCOPAD
External test pin: analog input to VCO
PLLVDDPAD
External pin: provides isolated PLL Vdd supply
PLLVSSPAD
External pin: provides isolated PLL Vss supply
Equivalent Gates
PLL Block
Test logic
PLLCORE
PLL Pads
Equivalent Gates
61.4
Corner Cell
2 I/O Pads+ 2 Power Pads
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