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參數(shù)資料
| 型號(hào)： | PLS173N |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | Programmable logic array 22 】 42 】 10 |
| 中文描述： | OT PLD, 30 ns, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 73K |
| 代理商： | PLS173N |
Philips Semiconductors Programmable Logic Devices
Product specification
PLS173
Programmable logic array
(22
×
42
×
10)
October 22, 1993
30
LOGIC PROGRAMMING
The PLS173 is fully supported by industry
standard (JEDEC compatible) PLD CAD
tools, including Philips Semiconductors
SNAP, Data I/O Corporation’s ABEL
, and
Logical Devices Incorporated’s CUPL
design software packages.
All packages allow Boolean and state
equation entry formats. SNAP, ABEL and
CUPL also accept, as input, schematic
capture format.
PLS173 logic designs can also be generated
using the program table entry format detailed
on the following pages. This program table
entry format is supported by the Philips
Semiconductors SNAP PLD design software
package.
To implement the desired logic functions, the
state of each logic variable from logic
equations (I, B, O, P, etc.) is assigned a
symbol. The symbols for TRUE,
COMPLEMENT, INACTIVE, PRESET, etc.,
are defined below.
PROGRAMMING AND
SOFTWARE SUPPORT
Refer to Section 9
(Development Software)
and Section 10
(Third-Party
Programmer/Software Support)
of this data
handbook for addtional information.
OUTPUT POLARITY – (B)
AND ARRAY – (I, B)
CODE
O
STATE
INACTIVE
1, 2
CODE
H
STATE
CODE
STATE
I, B
CODE
STATE
I, B
L
–
P, D
I, B
I, B
I, B
P, D
I, B
I, B
I, B
P, D
I, B
I, B
I, B
P, D
I, B
I, B
I, B
DON’T CARE
OR ARRAY – (B)
VIRGIN STATE
A factory shipped virgin device contains all
fusible links intact, such that:
1. All outputs are at “H” polarity.
2. All P
n
terms are disabled.
3. All P
n
terms are active on all outputs.
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused
(inactive) AND gates P
, D
.
2. Any gate P
, D
will be unconditionally inhibited if both the True and Complement of any input
(I, B) are left intact.
ABEL is a trademark of Data I/O Corp.
CUPL is a trademark of Logical Devices, Inc.
CODE
ACTIVE LEVEL
(INVERTING)
L
CODE
ACTIVE LEVEL
HIGH
1
(NON-NVERTING)
H
S
X
B
S
X
B
CODE
INACTIVE
A
CODE
P
n
STATUS
ACTIVE
1
P
S
P
n
STATUS
P
S
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PLS173N-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| PLS179/BLA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| PLS179A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| PLS179N | 制造商:NXP Semiconductors 功能描述:Simple, Programmable Logic Sequencer, 24 Pin, Plastic, DIP |
| PLS1A151MDL4 | 功能描述:鋁有機(jī)聚合物電容器 RoHS:否 制造商:Panasonic Electronic Components 電容:470 uF 容差:20 % 電壓額定值:2.5 V ESR:4.5 mOhms 工作溫度范圍:- 40 C to + 105 C 端接類型:SMD/SMT 外殼直徑: 外殼長(zhǎng)度:7.3 mm 外殼寬度:4.3 mm 外殼高度:1.9 mm 封裝:Reel |
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