參數(shù)資料
型號(hào)： PLSI1016E80LJI
廠商： Lattice Semiconductor Corporation
英文描述： High-Density Programmable Logic
中文描述： 高密度可編程邏輯
文件頁(yè)數(shù)： 12/15頁(yè)
文件大?。?/td> 208K
代理商： PLSI1016E80LJI
12
1996 ISP Encyclopedia
Specifications
ispLSI and pLSI 1016E
Input - This pin performs two functions. When
ispEN
is logic low, it functions
as an input pin to load programming data into the device. It is a dedicated
input pin when
ispEN
is logic high.SDI/IN0 also is used as one of the two
control pins for the isp state machine.
Input - This pin performs two functions. When
ispEN
is logic low, it functions
as a pin to control the operation of the isp state machine. It is a dedicated
input pin when
ispEN
is logic high.
Output/Input - This pin performs two functions. When
ispEN
is logic low, it
functions as an ouput pin to read serial shift register data. It is a dedicated
input pin when
ispEN
is logic high.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all the GLBs on the device.
This pin performs two functions:
- Dedicated clock input. This clock input is brought into the Clock
Distribution Network, and can optionally be routed to any GLB and/or
I/O cell on the device.
- Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO and
SCLK controls become active.
This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.
Input/Output Pins - These are the general purpose I/O pins used by the logic
array.
NAME
Table 2-0002C-16-isp
DESCRIPTION
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
GOE 0/IN 3
Y1/
RESET
Y0
SDI*/IN 0
ispEN
**/NC
MODE*/IN 2
GND
Vcc
VCC
SDO*/IN 1
Input - This pin performs two functions. When
ispEN
is logic low, it
functions as a clock pin for the Serial Shift Register. It is a dedicated clock
input when
ispEN
is logic high. This clock input is brought into the Clock
Distribution Network, and can optionally be routed to any GLB and/or I/O
cell on the device.
SCLK*/Y2
Ground (GND)
PLCC
PIN NUMBERS
16,
20,
26,
30,
38,
42,
4,
8,
15,
19,
25,
29,
37,
41,
3,
7,
17,
21,
27,
31,
39,
43,
5,
9,
18,
22,
28,
32,
40,
44,
6,
10
2
35
11
14
13
36
1,
12,
24
33
23
34
* ispLSI 1016E only
**
ispEN
for ispLSI 1016E; NC for pLSI 1016E must be left floating or tied to Vcc, must not be grounded or tied
to any other signal.
TQFP
PIN NUMBERS
10,
14,
20,
24,
32,
36,
42,
2,
9,
13,
19,
23,
31,
35,
41,
1,
11,
15,
21,
25,
33,
37,
43,
3,
12,
16,
22,
26,
34,
38,
44,
4
40
29
5
8
7
30
17,
6,
18
27
39
28
Pin Description
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PLSI1016E80LT44 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic
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PLSI1024-60LJ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD
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