參數(shù)資料
型號: PLSI1032E-100LJ
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: High-Density Programmable Logic
中文描述: EE PLD, 12.5 ns, PQCC84
封裝: PLASTIC, LCC-84
文件頁數(shù): 7/16頁
文件大?。?/td> 212K
代理商: PLSI1032E-100LJ
7
Specifications
ispLSI and pLSI 1032E
GRP Delay, 32 GLB Loads
t
iobp
t
iolat
t
iosu
t
ioh
t
ioco
t
ior
t
din
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/1032E
Inputs
UNITS
-100
MAX.
MIN.
MIN.
MAX.
DESCRIPTION
#
2
PARAM.
22 I/O Register Bypass
23 I/O Latch Delay
24 I/O Register Setup Time before Clock
25 I/O Register Hold Time after Clock
26 I/O Register Clock to Out Delay
27 I/O Register Reset to Out Delay
28 Dedicated Input Delay
ns
ns
ns
ns
ns
ns
ns
t
grp32
GLB
t
4ptbpc
t
4ptbpr
33
ns
t
1ptxor
t
20ptxor 37 20 Prod. Term/XOR Path Delay
t
xoradj
38 XOR Adjacent Path Delay
t
gbp
39 GLB Register Bypass Delay
t
gsu
40 GLB Register Setup Time before Clock
t
gh
41 GLB Register Hold Time after Clock
t
gco
42 GLB Register Clock to Output Delay
t
gro
43 GLB Register Reset to Output Delay
t
ptre
44 GLB Prod.Term Reset to Register Delay
t
ptoe
45 GLB Prod. Term Output Enable to I/O Cell Delay
t
ptck
46 GLB Prod. Term Clock Delay
ORP
t
orp
47 ORP Delay
t
orpbp
48 ORP Bypass Delay
36 1 Prod.Term/XOR Path Delay
ns
ns
ns
ns
ns
ns
ns
3
ns
ns
ns
ns
GRP
t
grp1
34 4 Prod.Term Bypass Path Delay (Combinatorial)
ns
35 4 Prod. Term Bypass Path Delay (Registered)
ns
ns
ns
t
grp16
32 GRP Delay, 16 GLB Loads
ns
t
grp8
31 GRP Delay, 8 GLB Loads
ns
t
grp4
30 GRP Delay, 4 GLB Loads
ns
29 GRP Delay, 1 GLB Load
ns
0.0
-125
0.1
4.5
2.9
3.0
0.0
0.3
1.9
4.6
4.6
2.3
3.8
3.6
5.0
5.0
0.4
2.3
4.9
3.9
5.4
4.0
3.9
4.0
1.0
0.0
2.8
2.3
2.0
1.8
0.5
5.8
3.5
3.5
0.0
0.3
2.3
5.0
5.0
2.7
4.2
4.6
5.8
6.3
1.0
2.5
6.2
4.5
7.2
4.7
5.3
5.3
1.0
3.0
2.4
2.4
1.9
Internal Timing Parameters
1
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