- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368051 > PLSI1032E-100LJ (Lattice Semiconductor Corporation) High-Density Programmable Logic PDF資料下載
參數(shù)資料
| 型號(hào)： | PLSI1032E-100LJ |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High-Density Programmable Logic |
| 中文描述： | 高密度可編程邏輯 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 212K |
| 代理商： | PLSI1032E-100LJ |
13
Specifications
ispLSI and pLSI 1032E
Pin Description
Input - This pin performs two functions. When
ispEN
is logic low, it functions
as pin to control the operation of the isp state machine. It is a dedicated
input pin when
ispEN
is logic high.
Output/Input - This pin performs two functions. When
ispEN
is logic low, it
functions as an output pin to read serial shift register data. It is a dedicated
input pin when
ispEN
is logic high.
Input - This pin performs two functions. When
ispEN
is logic low, it functions
as a clock pin for the Serial Shift Register. It is a dedicated input pin when
ispEN
is logic high.
This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.
This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.
Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any GLB on the device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
Input/Output Pins - These are the general purpose I/O pins used by the logic
array.
NAME
Table 2-0002A/1032E
PLCC PIN
NUMBERS
26,
30,
34,
38,
45,
49,
57,
68,
72,
76,
80,
3,
7,
11,
15,
16,
DESCRIPTION
27,
31,
35,
39,
46,
50,
54,
58,
69,
73,
77,
81,
4,
8,
12,
28,
32,
36,
40,
47,
51,
55,
59,
70,
74,
78,
82,
5,
9,
13,
17,
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
29,
33,
37,
41,
48,
52,
56,
60,
71,
75,
79,
83,
6,
10,
14,
18
66
Y1
20
Y0
42
MODE/IN 1
2
Ground (GND)
Vcc
GND
VCC
21, 65
NC
1
GOE 0/IN 4
3
Dedicated input pins to the device.
IN 6, IN 7
GOE 1/IN 5
3
2,
84
67
19
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO and
SCLK options become active.
Input - This pin performs two functions. When
ispEN
is logic low, it functions
as an input pin to load programming data into the device. SDI/IN 0 is also
used as one of the two control pins for the isp state machine. It is a
dedicated input pin when
ispEN
is logic high.
23
ispEN/NC
1,2
25
SDI/IN 0
2
44
SDO/IN 2
2
61
SCLK/IN 3
2
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the
device.
24
RESET
Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any GLB and/or any I/O cell on the
device.
Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any I/O cell on the device.
63
Y2
62
Y3
1,
22,
43,
64
12,
1,
26,
51,
76,
64
2, 24, 25, No connect.
27, 49, 50,
52, 74, 75,
77, 99, 100
1. NC pins are not to be connected to any ative signals, Vcc or GND.
2. Pins have dual function capability for ispLSI 1032E only.
3. Pins have dual function capability which is software selectable.
TQFP PIN
NUMBERS
17,
21,
29,
33,
40,
44,
48,
56,
67,
71,
79,
83,
90,
94,
98,
6,
7,
18,
22,
30,
34,
41,
45,
53,
57,
68,
72,
80,
84,
91,
95,
3,
19,
23,
31,
35,
42,
46,
54,
58,
69,
73,
81,
85,
92,
96,
4,
8,
20,
28,
32,
36,
43,
47,
55,
59,
70,
78,
82,
86,
93,
97,
5,
9
65
11
37
89,
87
66
10
14
16
39
60
15
62
61
13, 38,
63,
88
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PLSI2032-110LJ | 52Mbps Precision Delay RS485 Fail-Safe Transceivers; Package: SO; No of Pins: 8; Temperature Range: 0°C to +70°C |
| PLSI2032-110LT44 | Electrically-Erasable Complex PLD |
| PLSI2032-135LJ | 100Mbps RS485 Hot Swapable Quad Drivers; Package: SO; No of Pins: 16; Temperature Range: 0°C to +70°C |
| PLSI2032-135LT44 | Electrically-Erasable Complex PLD |
| PLSI2032-150LJ | Electrically-Erasable Complex PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PLSI1032E125LJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| PLSI1032E-125LJ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
| PLSI1032E70LJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| PLSI1032E-70LJ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
| PLSI1032E80LJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。