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參數(shù)資料
| 型號(hào)： | PLUS153DN |
| 廠(chǎng)商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | PLD |
| 英文描述： | Programmable logic arrays 18 】 42 】 10 |
| 中文描述： | OT PLD, 12 ns, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-20 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 72K |
| 代理商： | PLUS153DN |
Philips Semiconductors Programmable Logic Devices
Product specification
PLUS153B/D
Programmable logic arrays
(18
×
42
×
10)
October 22, 1993
13
AC ELECTRICAL CHARACTERISTICS
0
°
C
≤
T
amb
≤
+75
°
C, 4.75V
≤
V
CC
≤
5.25V, R
1
= 300
, R
2
= 390
LIMITS
SYMBOL
PARAMETER
FROM
TO
TEST
PLUS153B
PLUS153D
UNIT
CONDITION
MIN
TYP
MAX
MIN
TYP
MAX
t
PD
Propagation Delay
2
Input +/–
Output +/–
C
L
= 30pF
11
15
10
12
ns
t
OE
Output Enable
1
Input +/–
Output –
C
L
= 30pF
11
15
10
12
ns
t
OD
Output Disable
1
Input +/–
Output +
C
L
= 5pF
11
15
10
12
ns
NOTES:
1. For 3-State output; output enable times are tested with C
= 30pF to the 1.5V level, and S
is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with C
= 5pF. High-to-High impedance tests are made to an output
voltage of V
= (V
– 0.5V) with S
open, and Low-to-High impedance tests are made to the V
T
= (V
OL
+ 0.5V) level with S
1
closed.
2. All propagation delays are measured and specified under worst case conditions.
VOLTAGE WAVEFORMS
MEASUREMENTS:
All circuit delays are measured at the +1.5V level
of inputs and outputs, unless otherwise specified.
90%
10%
5ns
5ns
5ns
5ns
90%
10%
+3.0V
+3.0V
0V
0V
t
R
t
F
Input Pulses
TIMING DEFINITIONS
SYMBOL
PARAMETER
t
PD
Propagation delay between
input and output.
t
OD
Delay between input change
and when output is off (Hi-Z
or High).
t
OE
Delay between input change
and when output reflects
specified output level.
TEST LOAD CIRCUIT
TIMING DIAGRAM
+5V
C
L
R
1
R
2
S
1
GND
B
Z
B
Y
INPUTS
I0
I7
B
W
B
X
OUTPUTS
C
2
C
1
DUT
NOTE:
C
1
and C
2
are to bypass V
CC
to GND.
V
CC
+3V
0V
V
OH
V
OL
I, B
B
t
PD
1.5V
1.5V
1.5V
1.5V
1.5V
t
OD
t
OE
V
T
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