參數(shù)資料
型號(hào): PLUS16R6-7A
廠商: NXP SEMICONDUCTORS
元件分類: PLD
英文描述: PAL devices
中文描述: OT PLD, 10 ns, PQCC20
文件頁數(shù): 11/16頁
文件大?。?/td> 160K
代理商: PLUS16R6-7A
Philips Semiconductors Programmable Logic Devices
Product specification
PLUS16R8D/-7 SERIES
PAL devices
16L8, 16R8, 16R6, 16R4
September 10, 1993
46
AC ELECTRICAL CHARACTERISTICS
R
1
= 200
, R
2
= 390
, 0
°
C
T
amb
+75
°
C, 4.75
V
CC
5.25V
LIMITS
SYMBOL
PARAMETER
FROM
TO
–7
D
UNIT
MIN
1
TYP
MAX
MIN
1
MAX
Pulse Width
t
CKH
Clock High
CK+
CK–
5
7
ns
t
CKL
Clock Low
CK–
CK+
5
7
ns
t
CKP
Period
CK+
CK+
10
14
ns
Setup & Hold time
t
IS
Input
Input or
feedback
CK+
7
9
ns
t
IH
Input
CK+
Input or
feedback
0
0
ns
Propagation delay
t
CKO
Clock
CK
±
Q
±
3
6.5
3
7.5
ns
t
CKF
Clock
3
CK
±
Q
3
6.5
ns
t
PD
Output (16L8, R6, R4)
2
I, B
Output
3
7.5
3
10
ns
t
OE1
Output enable
4
OE
Output enable
3
8
3
10
ns
t
OE2
Output enable
4,5
I
Output enable
3
10
3
10
ns
t
OD1
Output disable
4
OE
Output disable
3
8
3
10
ns
t
OD2
Output disable
4,5
I
Output disable
3
10
3
10
ns
t
SKW
Output
Q
Q
1
1
ns
t
PPR
Power-Up Reset
V
CC
+
Q+
10
10
ns
Frequency (16R8, R6, R4)
No feedback 1/ (t
CKL
+ t
CKH
)
6
Internal feedback 1/ (t
IS
+ t
CKF
)
6
External feedback 1/ (t
IS
+ t
CKO
)
6
For definitions of the terms, please refer to the Timing/Frequency Definitions tables.
NOTES:
1. CL = 0pF while measuring minimum output delays.
2. t
PD
test conditions: CL = 50pF (with jig and scope capacitance), V
IH
= 3V, V
IL
= 0V, V
OH
= V
OL
= 1.5V.
3. t
CKF
was calculated from measured Internal f
MAX
.
4. For 3-State output; output enable times are tested with C
L
= 50pF to the 1.5V level, and S
1
is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with C
L =
5pF. High-to-High impedance tests are made to an output
voltage of V
= (V
OH
– 0.5V) with S
open, and Low-to-High impedance tests are made to the V
T
= (V
OL
+ 0.5V) level with S
1
closed.
5. Same function as t
OE1
and t
OD1,
with the difference of using product term control.
6. Not 100% tested, but calculated at initial
characterization and at any time a modification in design takes place which may affect the
frequency.
100
71.4
MHz
f
MAX
90
64.5
MHz
74
60.6
MHz
*
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