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參數(shù)資料
| 型號： | PLX9030 |
| 英文描述： | SmartTarget I/O Accelerator|PCI9030 Design Note Rev.1.0 |
| 中文描述： | SmartTarget的I / O加速器| PCI9030設計筆記Rev.1.0 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 104K |
| 代理商： | PLX9030 |
9222
A. Product Status
PCI 9030
Design Notes Rev. 1.0
December 2001
Product
PCI9030
PCI9030
Revision
PCI9030-AA60PI
PCI9030-AA60BI
Description
Samples
Mar 2000
Mar 2000
Production
April 2000
April 2000
Released 176-pin PQFP Product
Released 180-pin BGA Product
B. Documentation Status
Document
Data Book
C. Design Notes
1. Power Management Interface Specification version support
Design Issue:
The PCI 9030 Data Book indicates compliance with the PCI
Power Management Interface Specification revision 1.1, however the PMC
register description is compliant with revision 1.0. The PCI 9030 can support
either revision. The only differences between these revisions, with respect to
PCI 9030 support, are the Version bits [2:0] value (programmable by EEPROM),
and the descriptions for bits [8:6, 4] for which the values are read-only and return
a value of 0 regardless of revision. The Version bits value (001b or 010b), which
has no effect on PCI 9030 operation, is used by software to determine PMC
register format.
Recommendation:
PMC register descriptions for revisions 1.0 and 1.1 are
listed below. If revision 1.1 rather than revision 1.0 is to be supported, program
the serial EEPROM with the Version value (010b) to overwrite the PMC register
default value, by changing the 32-bit value at EEPROM offset 18h from
48014801h to 48024801h.
Revision
1.2
Description
PCI 9030 Data Book
Date
December 2001
Document number: 9030-SIL-DN-P0-1.0
-1-
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