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參數(shù)資料
| 型號(hào)： | PLX9050 |
| 英文描述： | Target Chip|PCI9050 Errata Rev. 1.3 |
| 中文描述： | 目標(biāo)芯片| PCI9050勘誤表1.3牧師 |
| 文件頁數(shù)： | 2/2頁 |
| 文件大小： | 104K |
| 代理商： | PLX9050 |
Register 10-27. (PMC; PCI:42h) Power Management Capabilities
(PCI Power Mgmt. r1.0)
Bit
Description
Read
Write
Value after
Reset
2:0
Version.
The value 001 indicates compliance with
PCI Power
Mgmt. r1.0.
PCI Clock Required for PME# Signal.
When set to 1,
indicates a function relies on PCI clock presence for PME#
operation. The PCI 9030 does not require the PCI clock for
PME#, so this bit should set to 0.
Auxiliary Power Source.
Because the PCI 9030 does not
support PME# while in a D
3
cold state, this bit is always set to 0.
Not Supported.
Device-Specific Initialization (DSI).
When set to 1, the PCI
9030 requires special initialization following a transition to a D
0
uninitialized state before a generic class device driver is able to
use it.
Reserved.
D
1
_Support.
When set to 1, the PCI 9030 supports the D
1
power state.
Not Supported.
D
2
_Support.
When set to 1, the PCI 9030 supports the D
2
power state.
Not Supported.
PME Support.
Indicates power states in which the PCI 9030
may assert PME#. Values:
XXXX1 = PME# can be asserted from D
0
XXXXX = The PCI 9030 does not support the D
1
power state
XXXXX = The PCI 9030 does not support the D
2
power state
X1XXX = PME# can be asserted from D
3hot
XXXXX = PME# cannot be asserted from D
3cold
Yes
Serial
EEPROM
001
3
Yes
Serial
EEPROM
0
4
Yes
No
0
5
Yes
Serial
EEPROM
0
8:6
Yes
No
000
9
Yes
No
0
10
Yes
No
0
15:11
Yes
[14:11]:
Serial
EEPROM
[15]: No
01001
Register 10-27. (PMC; PCI:42h) Power Management Capabilities
(PCI Power Mgmt. r1.1)
Bit
Description
Read
Write
Value after
Reset
2:0
Version.
The default value 001 indicates compliance with
PCI
Power Mgmt. r1.0
. To instead indicate PMC register format
compliance with Revision 1.1, this value should be set to 010.
PCI Clock Required for PME# Signal.
When set to 1,
indicates a function relies on PCI clock presence for PME#
operation. The PCI 9030 does not require the PCI clock for
PME#, so this bit should set to 0.
Reserved.
Device-Specific Initialization (DSI).
When set to 1, the PCI
9030 requires special initialization following a transition to a D
0
uninitialized state before a generic class device driver is able to
use it.
Aux_Current.
Supported by way of the PMDATA register per
PCI Power Mgmt. r1.1.
D
1
_Support.
When set to 1, the PCI 9030 supports the D
1
power state.
Not Supported.
D
2
_Support.
When set to 1, the PCI 9030 supports the D
2
power state.
Not Supported.
PME Support.
Indicates power states in which the PCI 9030
may assert PME#. Values:
XXXX1 = PME# can be asserted from D
0
XXXXX = The PCI 9030 does not support the D
1
power state
XXXXX = The PCI 9030 does not support the D
2
power state
X1XXX = PME# can be asserted from D
3hot
XXXXX = PME# cannot be asserted from D
3cold
Yes
Serial
EEPROM
001
3
Yes
Serial
EEPROM
0
4
Yes
No
0
5
Yes
Serial
EEPROM
0
8:6
Yes
No
000
9
Yes
No
0
10
Yes
No
0
15:11
Yes
[14:11]:
Serial
EEPROM
[15]: No
01001
Copyright 2001 by PLX Technology, Inc. All rights reserved. PLX is a trademark of PLX Technology, Inc. which may
be registered in some jurisdictions. All other product names that appear in this material are for identification purposes
only and are acknowledged to be trademarks or registered trademarks of their respective companies. Information
supplied by PLX is believed to be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any errors
that may appear in this material. PLX Technology reserves the right, without notice, to make changes in product design
or specification.
Document number: 9030-SIL-DN-P0-1.0
-2-
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