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參數(shù)資料
| 型號： | PM7339 |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Quad Cell Delineation Block Device |
| 中文描述： | ATM NETWORK INTERFACE, PBGA256 |
| 封裝： | 27 X 27 MM, 1.45 MM HEIGHT, SBGA-256 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 45K |
| 代理商： | PM7339 |
PM7339
PMC-Sierra,Inc.
Quad Cell Delineation Block Device
S/UNI-CDB
PMC-2000367 (R4)
PROPRIETARY AND CONFIDENTIAL TO PMC
-
SIERRA, INC., AND FOR ITS CUSTOMERS
’
INTERNAL USE
Copyright PMC
-
Sierra, Inc. 2001
FEATURES
Quad cell delineation block operating
up to a maximum rate of 52 Mbit/s.
Provides a UTOPIA Level 2-
compatible ATM-PHY Interface.
Implements the Physical Layer
Convergence Protocol (PLCP) for DS1
transmission systems according to the
ATM Forum User Network Interface
specification and ANSI TA-TSY-
000773, TA-TSY-000772, and E1
transmission systems according to the
ETSI 300-269 and ETSI 300-270.
Supports SMDS PLCP and ATM Direct
Mapping into various rate transmission
systems in the following formats:
E1 (2.048 Mbit/s) in CRC-4 and
PCM30;
T1 (1.544 Mbit/s) in ESF and SF;
Arbitrary Cell Rate (up to 52 Mbit/s)
with ATM Direct Mapping only.
Uses the PMC-Sierra PM4341 T1XC,
PM4344 TQUAD, PM6341 E1XC, and
PM6344 EQUAD T1 and E1
framer/line interface chips for DS-1
and E1 applications.
Provides programmable pseudo-
random test pattern generation,
detection and analysis features.
Provides performance monitoring
counters suitable for accumulation
periods of up to 1 second.
RECEIVER SECTION
Provides PLCP frame synchronization,
path overhead extraction and cell
extraction for DS1 and E1 PLCP
formatted streams.
Provides a 50 MHz 8-bit wide or 16-bit
wide UTOPIA FIFO buffer in the
receive path with parity support, and
multi-PHY (Level 2) control signals.
Provides ATM framing using cell
delineation. ATM cell delineation may
optionally be disabled to allow all cell
bytes to pass regardless of cell
delineation status.
Provides cell descrambling, header
check sequence (HCS) error detection,
idle cell filtering, header descrambling
(for use with PPP packets), and
accumulates the number of received
idle cells, the number of received cells
written to the FIFO and the number of
HCS errors.
Provides a four cell FIFO for rate
decoupling between the line, and a
higher layer processing entity. FIFO
latency may be reduced by changing
the number of operational cell FIFOs.
Provides programmable pseudo-
random test-sequence detection and
analysis features.
TRANSMITTER SECTION
Provides a 50 MHz 8-bit wide or 16-bit
wide Utopia FIFO buffer in the transmit
path with parity support and multi-PHY
(Level 2) control signals.
Provides optional ATM cell scrambling,
header scrambling (for use with PPP
packets), HCS generation/insertion,
programmable idle cell insertion,
diagnostics features and accumulates
transmitted cells read from the FIFO.
CPPM
PLCP/Cell Perf.
Monitor
P
RXCP_50
Rx
Cell
Processor
T
T
T
T
T
T
R
L
R
R
R
F
TCLK[4:1]
TDATO[4:1]
TOHM[4:1]
JTAG Test
Access
Port
T
T
T
T
T
D
I
A
R
A
C
W
R
Microprocessor
Interface
SPLT
Transmit ATM
and
PLCP Framer
TXCP_50
Tx
Cell
Processor
TXFF
Tx
4 Cell
FIFO
RXFF
Rx
4 Cell
FIFO
ATM/SPLR
Receive ATM
and PLCP
Framer
RCLK[4:1]
RDATI[4:1]
ROHM[4:1]
DTCA[4:1]
TDAT[15:0]
TPRTY
TSOC
TCA
TADR[4:0]
TENB
TFCLK
PHY_ADR[2:0]
ATM8
RFCLK
RENB
RADR[4:0]
RCA
RSOC
RPRTY
RDAT[15:0]
DRCA[4:1]
System
I/F
BLOCK DIAGRAM
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