參數(shù)資料
型號(hào): PMS430E337
英文描述: 16-Bit Ultra-Low-Power Microcontroller. 32kB EPROM. 1KB RAM. USART. HW multiplier. 120 segment LCD
中文描述: 16位超低功耗微控制器。具有32kB存儲(chǔ)器。 1kB的內(nèi)存。的USART。硬件乘法器。 120段LCD
文件頁數(shù): 21/29頁
文件大?。?/td> 411K
代理商: PMS430E337
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196C
DECEMBER 1998
REVISED MARCH 2003
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features
EN
D
See Note 1
See Note 2
See Note 2
See Note 1
GND
VCC
P1.4
P1.7
0
1
1
Interrupt
Edge
Select
EN
Set
Q
P1IE.x
P1IFG.x
P1IRQ.x
Interrupt
Flag
P1IES.x
P1SEL.x
Module X IN
P1IN.x
P1OUT.x
Module X OUT
Direction Control
From Module
P1DIR.x
P1SEL.x
Pad Logic
Bus Keeper
TControl
Fuse
60 k
Typical
GND
Fuse
Blow
VPP_Internal
Control By JTAG
0
TDO
Controlled By JTAG
P1.x
TDI
P1.x
TST
TST
TMS
TST
TCK
TST
Controlled by JTAG
TS
T
P1.x
P1.x
P1.7/TDI/TDO
P1.6/TDI
P1.5/TMS
P1.4/TCK
Test/VPP
NOTES:The est pin should be protected rom potential EMI and
ESD voltage spikes. This may require a smaller
external pulldown resistor in some applications.
x = Bit identifier, 4 to 7 for port P1
During programming activity and during blowing
the fuse, the pin TDO/TDI is used to apply the test
input for JTAG circuitry.
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
Module X
IN
PnIE.x
PnIFG.x
PnIES.x
P1Sel.4
P1DIR.4
P1DIR.4
P1OUT.4
SMCLK
Out0 signal
Out1 signal
Out2 signal
P1IN.4
unused
P1IE.4
P1IFG.4
P1IES.4
P1Sel.5
P1DIR.5
P1DIR.5
P1OUT.5
P1IN.5
unused
P1IE.5
P1IFG.5
P1IES.5
P1Sel.6
P1DIR.6
P1DIR.6
P1OUT.6
P1IN.6
unused
P1IE.6
P1IFG.6
P1IES.6
P1Sel.7
Signal from or to Timer_A
NOTES:
1. Optional selection of pullup or pulldown resistors with ROM (masked) versions.
2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory.
P1DIR.7
P1DIR.7
P1OUT.7
P1IN.7
unused
P1IE.7
P1IFG.7
P1IES.7
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