
NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 6: Boot Module
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
6-215
The PNX15xx/952x Series Boot system also provides a host-assisted boot script for
standalone board system (i.e. not a PCI plug-in card) that use PNX15xx/952x Series
in host-assisted mode. Since the PCI bus of this standalone board system is not
visible by the rest of the world it is possible to assign a default value and let the host
driver recognize a PNX15xx/952x Series system with the following IDs:
Finally on a PCI bus the sizes for all the apertures must be given an unique physical
addresses at PCI BIOS device enumeration time (DRAM, MMIO and XIO for the
PNX15xx/952x Series). This is the work of the host PCI BIOS driver.
Remark: The aperture sizes are written at boot time into the PCI module MMIO
registers. The host PCI BIOS software retrieves the values by a write, followed by a
read to the PCI Configuration space base address registers. It then assigns a suitable
value to each base address. Refer to [2], Section 6.2.5.1, “Address Maps” for more
details.
A typical simplied board system is sketched in
Figure 3. The aperture allocation
seen in the
Figure 3 is an example of how the host BIOS can set the location of the
apertures.
Table 9: Host Conguration Sequence
Boot Script Content
Comments
0x1be4_0010
(0x7583<<10) | (dram_size<<7) | en_pci_arb
PCI Setup Register
Depends on GPIO[11:8]
0x1be4_006c
0x0009_1131
PCI Subsystem ID is 0x0009
PCI Subsystem Vendor ID is 0x1131
Figure 3:
System Memory Map and Block Diagram Conguration for PNX15xx/952x Series in Host-assisted
Mode
0xFFFF,FFFF
PNX15xx/
BOOT_MODE[7:0]
PCI Agent/Slave
DDR SDRAM
PCI-XIO Bus
All set by the host BIOS
PCI Agent/Slave
RAM
Flash
Host CPU
Bridge
Boot
EEPROM
(Optional)
I2C
BASE_14
MMIO_BASE
BASE_10
DRAM_BASE
0x0000,0000
8-128 MB XIO
8-256 MB DRAM
2 MB MMIO
BASE_18
XIO_BASE