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參數(shù)資料
| 型號(hào)： | PowerPC 602 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-bit implementation Reduced Instruction Set Computer (RISC) Microprocessors.(32位精簡(jiǎn)指令集微處理器) |
| 中文描述： | 32位執(zhí)行精簡(jiǎn)指令集計(jì)算機(jī)（RISC的）微處理器。（32位精簡(jiǎn)指令集微處理器） |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大?。?/td> | 122K |
| 代理商： | POWERPC 602 |
PowerPC 602
Microprocessor
Highlights
Control Unit
Dispatches one instruction per cycle
Supports superscalar execution
Branch folding mplemented
Retires up to one nstruction per cycle
Load/Store Unit
One cycle cache access
Speculative cacheable oads (for no data
dependencies)
Integer Unit
One cycle add, subtract, shift, or rotate
Hardware multiply and divide
32 x 32-bit general purpose registers
Floating-Point Unit
IEEE-754 compliant single-precision
operations
32 x 32-bit floating point registers
Cache Unit
Separate 4K nstruction and data caches,
2-way set associative
3-state coherency protocol
Physically addressed tag and cache
arrays
Copy-back or write-thru data cache
Data coherency n hardware
Memory Management Unit
Separate 32-entry nstruction and data TLBs
Separate nstruction and data BATs (4 each),
offer protection and translation for 128K - 4MB
of memory
32-bit PowerPC Architecture compliant mode
Additional protection-only-mode” offers
protection of up to 4MB per TLB
Bus Interface Unit
General purpose nterface for a wide range of
system configurations
Multiplexed 32-bit address and 64-bit data
bus
Powerful diagnostic and test nterfaces
through the Common On-Chip
Processor (COP) and IEEE 1149.1 (JTAG)
interface
Power Management Unit
Static ow-power design
Dynamic power management
Hardware support for power saving modes
Internal clock multiplier for operation at 2x and
3x of bus clock
Product Description
The PowerPC 602* is a 32-bit implementa-
tion of the PowerPC* family of Reduced
Instruction Set Computer (RISC) micropro-
cessors. It is intended for use in portable and
small form factor uniprocessor applications
such as PDAs. It achieves its performance
through concurrent execution of up to two
instructions per cycle in its four parallel
execution units: the fixed-point unit, floating
point unit, branch processing unit, and the
load/store unit. The low-power design of the
PowerPC 602 microprocessor, and the
power management features it incorporates,
offer competitive advantages in perfor-
mance-oriented, power-sensitive portable
applications.
The PowerPC Architecture* is derived from
the IBM Performance Optimized With
Enhanced RISC (POWER*) architecture. The
PowerPC Architecture shares all the benefits
of the POWER Architecture*, but is optimized
for single-chip implementation. The
PowerPC architecture is a major component
of the PowerOpen* environment.
The PowerPC Architecture offers a complete
range of processor solutions for computing
needs from embedded applications through
multi-processor mainframe systems. Its
unique combination of high performance,
wide operating systems applicability, and
small die size has resulted in its unprec-
edented success in the RISC computing
market.
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