參數(shù)資料
型號： PPC405CR-3BC133CZ
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： PowerPC 405CR Embedded Processor
中文描述： 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA316
封裝： 27 X 27 MM, PLASTIC, EBGA-316
文件頁數(shù)： 25/42頁
文件大小： 446K
代理商： PPC405CR-3BC133CZ
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
AMCC
25
External Master Peripheral Interface
PerClk
Peripheral clock to be used by an external master and by
synchronous peripheral slaves.
O
5V tolerant
3.3V LVTTL
ExtReset
Peripheral reset to be used by an external master and by
synchronous peripheral slaves.
O
5V tolerant
3.3V LVTTL
HoldReq
Hold Request, used by an external master to request ownership of
the peripheral bus.
I
5V tolerant
3.3V LVTTL
1, 5
HoldAck
Hold Acknowledge, used by the PPC405CR to transfer ownership of
peripheral bus to an external master.
O
5V tolerant
3.3V LVTTL
6
ExtReq
ExtReq is used by an external master to indicate it is prepared to
transfer data.
I
5V tolerant
3.3V LVTTL
1
ExtAck
ExtAck is used by the PPC405CR to indicate a data transfer cycle.
O
5V tolerant
3.3V LVTTL
6
HoldPri
Used by an external master to indicate the priority of a given external
master tenure.
I
5V tolerant
3.3V LVTTL
1
BusReq
Used when the PPC405CR needs to regain control of the peripheral
interface from an external master.
O
5V tolerant
3.3V LVTTL
PerErr
Used as an input to indicate that an external slave peripheral error
has occurred.
I
5V tolerant
3.3V LVTTL
1, 5
Internal Peripheral Interface
UARTSerClk
Serial clock. Used to provide an alternate clock to the internally
generated serial clock. Used in cases where the allowable internally
generated baud rates are not satisfactory. This input can be
individually connected to either UART.
I
5V tolerant
3.3V LVTTL
1
UART0_Rx
UART0 Receive (serial data in).
I
5V tolerant
3.3V LVTTL
1
UART0_Tx
UART0 Transmit (serial data out).
O
5V tolerant
3.3V LVTTL
6
UART0_DCD
UART0 Data Carrier Detect.
I
5V tolerant
3.3V LVTTL
1
UART0_DSR
UART0 Data Set Ready.
I
5V tolerant
3.3V LVTTL
1
UART0_CTS
UART0 Clear To Send.
I
5V tolerant
3.3V LVTTL
1
UART0_DTR
UART0 Data Terminal Ready.
O
5V tolerant
3.3V LVTTL
6
UART0_RTS
UART0 Request To Send.
O
5V tolerant
3.3V LVTTL
6
UART0_RI
UART0 Ring Indicator.
I
5V tolerant
3.3V LVTTL
1
UART1_Rx
UART1 Receive (serial data in).
I
5V tolerant
3.3V LVTTL
1
Table 6. Signal Functional Description (Sheet 3 of 5)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull-up or pull-down required.
7. Pull-up may be required. See “External Bus Control Signals” on page 22.
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PPC405CR-3BC200C 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 405CR Embedded Processor
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PPC405CR-3BC266C 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 405CR Embedded Processor
PPC405CR-3BC266CZ 制造商:AppliedMicro 功能描述:MPU 405CR RISC 32BIT 0.25UM 266MHZ 3.3V 316PIN EBGA - Tape and Reel
PPC405CR-3KC133C 制造商:AppliedMicro 功能描述:MPU 405CR RISC 32-Bit 0.25um 133MHz 3.3V 316-Pin EBGA Tray
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