參數(shù)資料
型號(hào): PPC405EP-3GB133C
廠(chǎng)商: APPLIEDMICRO INC
元件分類(lèi): 微控制器/微處理器
英文描述: PowerPC 405EP Embedded Processor
中文描述: 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385
封裝: 31 X 31 MM, PLASTIC, EBGA-385
文件頁(yè)數(shù): 45/50頁(yè)
文件大?。?/td> 373K
代理商: PPC405EP-3GB133C
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
AMCC
45
Table 14. I/O Specifications—Group 1 (Sheet 1 of 2)
Notes:
1.
PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns
for 33.33MHz.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter
selected. See the CPC0_EPCTL register
PowerPC 405EP Embedded Processor User’s Manual
.
3. For PCI, I
OH
is specified at 0.9OV
DD
and I
OL
is specified at 0.1OV
DD
. For all other interfaces, I
OH
is specified at 2.4V and I
OL
is specified at 0.4V.
Signal
Input (ns)
Output (ns)
Output Current (mA)
I
OH
(min)
Clock
Notes
Setup Time
(T
IS
min)
Hold Time
(T
IH
min)
Valid Delay
(T
OV
max)
Hold Time
(T
OH
min)
I
OL
(min)
PCI Interface
PCIAD31:00
PCIC3:0/BE3:0
PCIClk
PCIDevSel
PCIFrame
PCIGnt0/Req
PCIGnt1:2
PCIIDSel
PCIINT[PerWE]
PCIIRDY
PCIParity
PCIPErr
PCIReq0/Gnt
PCIReq1:2
PCIReset
PCISErr
PCIStop
PCITRDY
Ethernet Interface
EMC0MDClk
3
3
0
0
6
6
1
1
0.5
0.5
na
0.5
0.5
1.5
1.5
na
1.5
1.5
PCIClk
PCIClk
async
PCIClk
PCIClk
1
1
na
3
3
na
0
0
na
6
6
na
1
1
1
1
na
na
6
1
0.5
1.5
PCIClk
1
3
na
3
3
3
0
na
0
0
0
na
na
6
6
6
na
na
1
1
1
na
0.5
0.5
0.5
0.5
na
1.5
1.5
1.5
1.5
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
1
1
1
1
1
5
0
na
na
na
na
PCIClk
1
na
na
3
3
na
na
0
0
na
na
6
6
na
na
1
1
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
PCIClk
PCIClk
PCIClk
PCIClk
1
1
1
1
na
na
settable
1 OPB clock
period + 10ns
14
14
14
na
na
na
na
na
na
na
2
10.3
7.1
async
2
EMC0MDIO
100
0
1 OPB clock
period
5
5
5
na
na
na
na
na
na
na
10.3
7.1
EMC0MDClk
2
EMC0Tx0:1D3:0
EMC0Tx0:1En
EMC0Tx0:1Err
PHY0Col0:1
PHY0CrS0:1
PHY0Rx0:1Clk
PHY0Rx0:1D3:0
PHY0Rx0:1DV
PHY0Rx0:1Err
PHY0Tx0:1Clk
na
na
na
2
2
na
2
2
2
na
na
na
na
3
3
na
4
4
4
na
10.3
10.3
10.3
na
na
na
na
na
na
na
7.1
7.1
7.1
na
na
na
na
na
na
na
PHY0TxClk
PHY0TxClk
PHY0TxClk
PHY0RxClk
PHY0RxClk
async
PHY0RxClk
PHY0RxClk
PHY0RxClk
async
2
2
2
2
2
2
2
2
2
2
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