參數(shù)資料
型號(hào): PPC405EP-3GB133CZ
廠商: APPLIEDMICRO INC
元件分類: 微控制器/微處理器
英文描述: PowerPC 405EP Embedded Processor
中文描述: 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385
封裝: 31 X 31 MM, PLASTIC, EBGA-385
文件頁(yè)數(shù): 35/50頁(yè)
文件大小: 373K
代理商: PPC405EP-3GB133CZ
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
AMCC
35
TDO
Test data out.
O
5V tolerant
3.3V LVTTL
TCK
JTAG test clock. The frequency of this input can range from DC to
25MHz.
I
5V tolerant
3.3V LVTTL
1, 4
TRST
JTAG reset. TRST must be low at power-on to initialize the JTAG
controller.
I
5V tolerant
3.3V LVTTL
5
System Interface
SysReset
Main system reset. External logic can drive this bidirectional pin low
(minimum of 16 cycles) to initiate a system reset. A system reset can
also be initiated by software. Implemented as an open-drain output
(two states; 0 or open circuit).
I/O
5V tolerant
3.3V LVTTL
1, 2
SysErr
Set to 1 when a Machine Check is generated.
O
5V tolerant
3.3V LVTTL
6
Halt
Halt from external debugger.
I
5V tolerant
3.3V LVTTL
1, 2
GPIO00:31
General Purpose I/O. All of the GPIO signals are multiplexed with
other signals.
I/O
5V tolerant
3.3V LVTTL
1
TestEn
Test Enable. Used only for manufacturing tests. Pull down for normal
operation.
I
1.8V CMOS
w/pull-down
SysClk
Main system clock input.
I
3.3V LVTTL
[RejectPkt0:1]
External request to reject a packet.
I
5V tolerant
3.3V LVTTL
AV
DD
Clean voltage input for the PLL.
I
AGND
Clean Ground input for the PLL.
I
Trace Interface
[TS1E]
[TS2E]
Even Trace execution status. To access this function, software must
toggle a DCR bit
O
5V tolerant
3.3V LVTTL
1
[TS1O]
[TS2O]
Odd Trace execution status. To access this function, software must
toggle a DCR bit
O
5V tolerant
3.3V LVTTL
1
[TS3:6]
Trace status. To access this function, software must toggle a DCR bit
O
5V tolerant
3.3V LVTTL
1
[TrcClk]
Trace interface clock. Operates at half the CPU core frequency. To
access this function, software must toggle a DCR bit
O
5V tolerant
3.3V LVTTL
1
Power
GND
Ground
Note:
K10-K14, L10-L14, M10-M14, N10-N14, and P10-P14 are also
thermal balls.
na
na
na
OV
DD
Output driver voltage—3.3V.
na
na
na
Table 6. Signal Functional Description (Sheet 5 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 30.
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PPC405EP-3GB200C 制造商:AppliedMicro 功能描述:MPU 405EP RISC 32-Bit 0.18um 200MHz 3.3V 385-Pin EBGA Tray 制造商:AMCC 功能描述:MPU 405EP RISC 32BIT 0.18UM 200MHZ 3.3V 385PIN EBGA - Trays 制造商:AMCC 功能描述:AMCPPC405EP-3GB200C 32 Bit PowerPC
PPC405EP-3GB200CZ 制造商:AppliedMicro 功能描述:MPU 405EP RISC 32-Bit 0.18um 200MHz 3.3V 385-Pin EBGA T/R
PPC405EP-3GB266C 制造商:AppliedMicro 功能描述:MPU 405EP RISC 32-Bit 0.18um 266MHz 3.3V 385-Pin EBGA Tray 制造商:AMCC 功能描述:MPU 405EP RISC 32BIT 0.18UM 266MHZ 3.3V 385PIN EBGA - Trays 制造商:AMCC 功能描述:AMCPPC405EP-3GB266C 32 Bit PowerPC 制造商:Applied Micro Circuits Corporation 功能描述:MPU 405EP RISC 32-Bit 0.18um 266MHz 3.3V 385-Pin EBGA Tray
PPC405EP-3GB266CZ 制造商:AppliedMicro 功能描述:MPU 405EP RISC 32-Bit 0.18um 266MHz 3.3V 385-Pin EBGA T/R
PPC405EP-3GB333C 制造商:AppliedMicro 功能描述:MPU 405EP RISC 32-Bit 0.18um 333MHz 3.3V 385-Pin EBGA Tray 制造商:AMCC 功能描述:MPU 405EP RISC 32BIT 0.18UM 333MHZ 3.3V 385PIN EBGA - Trays