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參數(shù)資料
| 型號(hào)： | PPC440SP-RFC533C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PowerPC 440SP Embedded Processor |
| 中文描述： | 32-BIT, 533 MHz, RISC PROCESSOR, PBGA783 |
| 封裝： | 29 X 29 MM, 1 MM PITCH, PLASTIC, FCBGA-783 |
| 文件頁數(shù)： | 9/85頁 |
| 文件大?。?/td> | 615K |
| 代理商： | PPC440SP-RFC533C |
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PowerPC 440SP Embedded Processor
Revision 1.23 - Sept 26, 2006
Data Sheet
AMCC Proprietary
9
PowerPC 440 Processor Core
The PowerPC 440 processor core is designed for high-end applications such as RAID controllers, SAN, iSCSI,
routers, switches, printers, set-top boxes, and so on. It is the first processor core to implement the Book E
PowerPC embedded architecture and the first to use the 128-bit version of IBM’s on-chip CoreConnect Bus
Architecture.
Features include:
Up to 667MHz operation
PowerPC Book E architecture
32KB I-cache, 32KB D-cache
– Parity on Data and Tag address - checking of parity with error injection
Three logical regions in D-cache: Locked, Transient, and Normal
D-cache full-line flush capability
41-bit virtual address, 36-bit (64GB) physical address
Superscalar, out-of-order execution
Seven-stage pipeline
Three execution pipelines
Dynamic branch prediction
Memory management unit
– 64-entry, full associative, unified TLB with parity
– Separate instruction and data micro-TLBs
– Storage attributes for write-through, cache-inhibited, guarded, and big or little endian
Debug facilities
– Multiple instruction and data range breakpoints
– Data value compare
– Single step, branch, and trap events
– Non-invasive real-time trace interface
24 DSP instructions
– Single cycle multiply and multiply-accumulate
– 32 x 32 integer multiply
Internal Buses
The PowerPC 440SP Embedded Processor features three standard on-chip buses: the Processor Local Bus
(PLB), the On-Chip Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance,
high bandwidth cores such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the
DDR PCI-X bridge connect to the PLB. The OPB hosts lower data rate peripherals. The daisy-chained DCR
provides a lower bandwidth path for passing status and control information between the processor core and the
other on-chip cores.
The PLB has a Crossbar arbiter that supports data transfer between the PLB master and two slave segments
identified as the Low Latency (LL) and High Bandwidth (HB) segments. The LL segment allows PLB masters CPU
and I2O, that are adversely affected by latency, to communicate with slave devices with minimal latency. The HB
segment allows PLB masters DMA, XOR, and PCI to exchange large blocks of data with SDRAM and PCI without
interfering with the low latency PLB masters.
Bus features include:
PLB
– 128-bit Data implementation of the PLB architecture
– Separate and simultaneous read and write data paths
– 64-bit address
– Simultaneous control, address, and data phases
– Four levels of pipelining
– Byte enable capability supporting unaligned transfers
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| PPC440SP-RFC667C | PowerPC 440SP Embedded Processor |
| PPC440SP-RNC533C | PowerPC 440SP Embedded Processor |
| PPC440SP-RNC667C | PowerPC 440SP Embedded Processor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440SP-RFC667C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SP Embedded Processor |
| PPC440SP-RNC533C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SP Embedded Processor |
| PPC440SP-RNC667C | 制造商:AMCC 功能描述:AMCPPC440SP-RNC667C PWR PROCESSOR CORE |
| PPC-46 | 功能描述:電源變壓器 115/230Vac 50/60Hz 1.5VA RoHS:否 制造商:Triad Magnetics 功率額定值:12 VA 初級(jí)電壓額定值:115 V / 230 V 次級(jí)電壓額定值:12 V / 24 V 安裝風(fēng)格:SMD/SMT 一次繞組:Dual Primary Winding 二次繞組:Dual Secondary Winding 長(zhǎng)度:2.5 in 寬度:2 in 高度:1.062 in |
| PPC460EX-NUA1000T | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 1.2 GHZ, 2 10/100/1G ETHERNET, US - Trays |
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