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| 型號： | PPCSALESFACT |
| 英文描述： | PowerPC Processors At-A-Glance |
| 中文描述： | PowerPC處理器在一瞥 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 392K |
| 代理商： | PPCSALESFACT |
POWERPC G4 ARCHITECTURE: DELIVERING
PERFORMANCE ENHANCEMENT BEYOND
60X BUS MODE
Address and data bus streaming for reduced
cycle latency
– 60x bus requires a dead cycle between
back-to-back address tenures or data tenures.
– MPX bus supports both “address streaming”
and “data streaming”: A master may drive
consecutive address tenures or consecutive burst
data tenures without a dead cycle in between.
Data intervention for fewer memory accesses
– Snoop Hit Scenario: Processor “A” performs a
read operation; The target data is modified in
Processor “B’s” cache.
– 60x bus—Write to main memory and read from
main memory: “B” responds with a retry and
pushes the data to memory; “A” repeats the read
request and loads the data from memory.
– MPX bus—Single fast write on the bus: “B”
asserts the data ready signal and uses a data-only
transaction to supply the data directly to “A.”
Out-of-order transactions
– 60x bus: Data tenures must occur in the same
order as the associated address tenures.
– MPX bus: When a processor receives data
out-of-order, the processor uses an index value
(driven with the data) to associate the data on
the bus with a previous address tenure.
– Out-of-order transactions may hide the latency
of a slow memory or peripheral access.
MOTOROLA
7445*
PowerPC
Processors
7410
7441
7447*
7451
7455*
7457*
CPU Speed (MHz)
400–550
600–700
733–1000
733–1300
533–667
733–1000
733–1300
Bus Speed (MHz)
133
133
150/166
166/200
133
150/166
166/200
MPX Bus Support
Yes
Yes
Yes
Yes
Yes
Yes
Yes
L2 Cache (KB)
256
256
512
256
256
512
Backside Cache
Support (MB)
1 or 2
N/A
N/A
N/A
1 or 2
1 or 2
1, 2 or 4
Process
0.18μ 6LM
0.18μ 6LM
0.18μ 6LM
SOI
0.13μ 9LM
SOI
0.18μ 6LM
0.18μ 6LM
SOI
0.13μ 8LM
SOII
Pipeline
4 stage
7 stage
7 stage
7 stage
7 stage
7 stage
7 stage
SPECint95 (est.)
22.8 @
500 MHz
32.1 @
733 MHz
32.1 @
733 MHz
32.1 @
733 MHz
32.1 @
733 MHz
32.1 @
733 MHz
32.1 @
733 MHz
SPECfp95 (est.)
17 @
500 MHz
23.9 @
733 MHz
23.9 @
733 MHz
23.9 @
733 MHz
23.9 @
733 MHz
23.9 @
733 MHz
23.9 @
733 MHz
Other
Performance
1210 MIPS
@ 500 MHz
1617 MIPS
@ 700 MHz
1848 MIPS
@ 800 MHz
1848 MIPS
@ 800 MHz
1617 MIPS
@ 700 MHz
2310 MIPS
@ 1 GHz
2310 MIPS
@ 1 GHz
Dhrystone
MIPS/MHz
2.42
2.31
2.31
2.31
2.31
2.31
2.31
Address and Data
Bus Streaming
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Data Intervention
Support
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Out-of-Order
Transaction
Yes
Yes
Yes
Yes
Yes
Yes
Yes
AltiVec Support
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SMP Support
MESI
MESI
MESI
MESI
MESI
MESI
MESI
Instructions/Clock
3 (2+branch)
4 (3+branch)
4 (3+branch)
4 (3+branch)
4 (3+branch)
4 (3+branch)
4 (3+branch)
Typical Power
Consumption
5.3W @
500 MHz
11.5W @
600 MHz
For More Information On This Product,
Go to: www.freescale.com
11.2W @
800 MHz
6.5W @
900 MHz
11.7W @
600 MHz
11.2W @
800 MHz
7.5W @
1 GHz (est.)
F
Freescale Semiconductor, Inc.
n
.
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