參數(shù)資料
型號(hào)： PR31700
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 32-bit RISC Microprocessor(32位 RISC微處理器)
中文描述： 32-BIT, 75 MHz, RISC PROCESSOR, PQFP208
封裝： PLASTIC, LQFP-208
文件頁(yè)數(shù)： 8/36頁(yè)
文件大小： 378K
代理商： PR31700
Philips Semiconductors
Preliminary specification
PR31700
32-bit RISC microprocessor
1998 May 13
8
PIN FUNCTIONS
NAME
I/O
FUNCTIONS
Memory Pins
D(31:0)
I/O
These pins are the data bus for the system. 8-bit SDRAMs should be connected to bits 7:0 and 16-bit
SDRAMs and DRAMs should be connected to bits 15:0. All other 16-bit ports should be connected to bits
31:16. Of course, 32-bit ports should be connected to bits 31:0. These pins are normally outputs and only
become inputs during reads, thus no resistors are required since the bus will only float for a short period of
time during bus turn-around.
A(12:0)
O
These pins are the address bus for the system. The address lines are multiplexed and can be connected
directly to SDRAM and DRAM devices. To generate the full 26-bit address for static devices, an external
latch must be used to latch the signals using the ALE signal. For static devices, address bits 25:13 are
provided by the external latch and address bits 12:0 (directly connected from PR31700’s address bus) are
held afterward by PR31700 processor for the remainder of the address bus cycle.
ALE
O
This pin is used as the address latch enable to latch A(12:0) using an external latch, for generating the
upper address bits 25:13.
RD
*
O
This pin is used as the read signal for static devices. This signal is asserted for reads from /MCS3*-0*,
/CS3*-0*, /CARD2CS* and /CARD1CS* for memory and attribute space, and for reads from PR31700
processor accesses if SHOWPOSEIDON is enabled (for debugging purposes).
WE*
O
This pin is used as the write signal for the system. This signal is asserted for writes to /MCS3*-0*, /CS3*-0*,
/CARD2CS* and /CARD1CS* for memory and attribute space, and for writes to DRAM and SDRAM.
CAS0
*
(/WE0)
*
O
This pin is used as the CAS signal for SDRAMs, the CAS signal for D(7:0) for DRAMs, and the write enable
signal for D(7:0) for static devices.
CAS
*
(/WE1)
*
O
This pin is used as the CAS signal for D(15:8) for DRAMs and the write enable signal for D(15:8) for static
devices.
CAS2
*
(/WE2)
*
O
This pin is used as the CAS signal for D(23:16) for DRAMs and the write enable signal for D(23:16) for
static devices.
CAS3
*
(/WE3)
*
O
This pin is used as the CAS signal for D(31:24) for DRAMs and the write enable signal for D(31:24) for
static devices.
RAS0
*
RAS1
*
(/DCS1)
*
DCS0
*
O
This pin is used as the RAS signal for SDRAMs and the RAS signal for Bank0 DRAMs.
O
This pin is used as the chip select signal for Bank1 SDRAMs and the RAS signal for Bank1 DRAMs.
O
This pin is used as the chip select signal for Bank0 SDRAMs.
DCKE
O
This pin is used as the clock enable for SDRAMs.
DCLKIN
I
This pin must be tied externally to the DCLKOUT signal and is used to match skew for the data input when
reading from SDRAM and DRAM devices.
DCLKOUT
O
This pin is the (nominal) 73.728 MHz clock for the SDRAMs.
DQMH
O
This pin is the upper data mask for a 16-bit SDRAM configuration.
DQML
CS3–0
*
O
This pin is the lower data mask for a 16-bit SDRAM or 8-bit SDRAM configuration.
O
These pins are the Chip Select 3 through 0 signals. They can be configured to support either 32-bit or 16-bit
ports.
MCS3–0
*
CARD2CSH
*
,L
*
/CARD1CSH
*
,L
*
CARDREG
*
CARDIORD
*
CARDIOWR
*
CARDDIR
*
O
These pins are the Memory Card Chip Select 3 through 0 signals. They only support 16-bit ports.
O
These pins are the Chip Select signals for PCMCIA card slot 2.
O
These pins are the Chip Select signals for PCMCIA card slot 1.
O
This pin is the /REG* signal for the PCMCIA cards.
O
This pin is the /IORD* signal for the PCMCIA IO cards.
O
This pin is the /IOWR* signal for the PCMCIA IO cards.
O
This pin is used to provide the direction control for bi-directional data buffers used for the PCMCIA slot(s).
This signal will assert whenever /CARD2CSH* or /CARD2CSL* or /CARD1CSH* or /CARD1CSL* is
asserted and a read transaction is taking place.
CARD2WAIT
*
CARD1WAIT
*
*Active-low signal
I
This pin is the card wait signal from PCMCIA card slot 2.
I
This pin is the card wait signal from PCMCIA card slot 1.
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