AHA4540B-086PQI-G
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產(chǎn)品信息
AHA4540B
155 MBITS/SEC TURBO PRODUCT CODE
ENCODER/DECODER
The AHA4540 device is a single-chip Turbo FEATURES
Product Code (TPC) Forward Error Correction
(FEC) Encoder/Decoder capable of 155 Mbit/sec PERFORMANCE:
(OC-3) data rates (up to 200 Mbit/sec channel rates).
This device integrates both a TPC encoder and ? Maximum 200 Mbit/sec channel rate
decoder, and can be operated in a full duplex mode. ? Payload data rates of at least 155 Mbit/sec for
In addition to TPC coding, support is included for
helical interleaving, synchronization mark insertion code rates >0.7 and three iterations
and detection, CRC computation, scrambling, and ? Symbol rates up to 50 MSym/sec
higher order modulation symbol mapping. Figure 1 ? Encode Latency of less than 10 clocks
shows the functional BLOCK diagram. ? Integrated encoder/decoder;
The channel interface supports direct scrambler/descrambler; and
connection to various modulators and demodulators. interleaver/deinterleaver for full duplex operation
Support for an arbitrary constellation mapping is ? Supports enhanced Turbo Product Codes (eTPCs)
included with external logic. ? Corrections count and averaging for channel SNR
estimation
The encode path accepts byte-wide data,
computes and inserts a CRC, and scrambles the data FLEXIBILITY:
before TPC encoding. After the error correction
code (ECC) bits are inserted by the encoder, the data ? Code Rates from .25 to 0.98
is helically interleaved, and block synchronization ? Variable iterations up to 256 per block
marks are inserted to assist the decoder. Finally, the ? Block Sizes from 256 bits to 16 Kbits
data is mapped according to the constellation and ? Programmable code shortening supports exact
output from the device.
block sizes
The decoder accepts input symbols via the ? 32 bit CRC Insertion and Checking with
demodulated in-phase (I) and quadrature (Q)
components or alternately as soft metric inputs from programmable packet length
an external demodulator. An internal block
synchronizer searches for synchronization marks, CHANNEL INTERFACE:
rotating the input symbol phase as necessary. After
synchronization is achieved, the data is helically ? Accepts in-phase and quadrature (I & Q) inputs,
deinterleaved and decoded by the TPC decoder. The up to 8 bits each
output of the decoder is descrambLED, and the CRC
is computed to verify data integrity. Decoded data is ? Supports soft metric inputs at up to 4 soft metrics
output in a parallel, byte-wide fashion. of 4 bits each
Internal circuitry enables the transfer rate across ? Soft metric computation for BPSK, QPSK, 8-
all ports, generating a constant, non-burst data flow. PSK, 16-QAM, 64-QAM, and 256-QAM
In addition, control of an external VCO can be used
to generate data clocks, greatly simplifying system ? Supports additional modulation formats with
clocking issues. external logic
comtech aha corporation ? Encoder and decoder pass through modes
? Programmable packet and block level
synchronization
? Automatic phase ambiguity resolution
? Supports insertion and detection of sync marks up
to 32 bits in length
? 8-bit Parallel Data Input/Output
? Support for external VCO to generate data clocks
OTHERS:
? Intel or Motorola microprocessor interface
? 3.3V I/O, 1.8V core operation
? Commercial or industrial temperature rating
? RoHS compliant
This product is covered under multiple patents held or licensed by Comtech AHA Corp.
This product is covered by a Turbo Code Patent License from France Telecom - TDF -
Groupe des ecoles des telecommunications.
*Request the AHA4540B Product Specification for complete details.
comtech aha corporation
CODE TYPES
Table 1 shows a partial list of the codes supported by this product. Note that this is not a complete list
of base codes. In addition, each of the codes listed can be shortened to achieve smaller block size with only
minor changes to code rate.
Table 1: Partial Code List
CODE BLOCK SIZE DATA SIZE RATE CODING GAIN # ITERATIONS
AT 155 mBPS
(X)x(Y)x(Z) (bits) (bits) (dB)
(128,127)x(128,126)+ 16384 16002 0.977 4.3 4
(128,120)x(128,126)+
(128,120)x(128,120) 16384 15120 0.923 5.5 5
(64,57)x(16,15)x(16,15)
(128,127)x(64,62)+ 16384 14400 0.879 6.5 6
(128,120)x(64,62)+
(128,120)x(64,57) 16384 12825 0.783 6.9 4
(32,26)x(16,15)x(16,15)
(64,63)x(64,62)+ 8192 7874 0.961 4.4 4
(64,57)x(64,57)
(64,63)x(32,30)+ 8192 7440 0.908 5.5 4
(64,57)x(32,26)
(32,26)x(32,26) 8192 6840 0.84 6.5 5
8192 5850 0.714 7.2 4
4096 3906 0.954 4.5 3
4096 3249 0.793 6.9 4
2048 1890 0.923 4.5 3
2048 1482 0.724 6.9 3
1024 676 0.660 6.3 2
+ enhanced TPC (includes hyper diagonal axis).
Figure 1: Turbo Product Code Encoder/Decoder
ENCODER
ENC_DATA CRC Scrambler TPC Helical Sync Constellation XMIT_DATA
Insertion Encoder Interleaver
Insertion Mapper
DECODER
DEC_DATA CRC Descrambler TPC Helical Sync Soft REC_DATA
Verification Decoder Deinterleaver Detection Metric
Computation
uP_INT Microprocessor Interface,
Control and Status
Registers AHA4540
comtech aha corporation
FUNCTIONAL OVERVIEW
The channel encoder is designed to input data in When using internal soft metric computation,
a byte-wide fashion. This data is CRC encoded and the input data is an I and Q sample value for the
randomized before coding by the TPC encoder. given symbol. The soft metric computation engine
Synchronization marks are then inserted into the converts each I and Q sample to the soft metrics
data before it is mapped to a user programmable required by the TPC decoder.
constellation. The blocks may be bypassed if not
needed. When soft metric computation is disabled, the
input data is a soft metric value for each bit in the
Each symbol for modulation is output TPC block with up to 4 bits transferred on each
synchronous to the transmit clock, with one symbol clock edge. Each bit would consist of up to 4
transferred for each rising edge of the clock. The confidence bits per data bit. If enabled, all
format for output data depends on the modulation synchronization is controlled by the device
format chosen. including phase ambiguity resolution. Output is in a
byte wide fashion with packet start, end and error
The channel decode data path begins with signals.
received symbols input to the device synchronous to
the receive clock, with one symbol transferred per
rising edge.
CODE PERFORMANCE
Figure 2: Bit Error Rate (BER) Performance (simulated) on a QPSK Channel
bpsk_oc3
comtech aha corporation
Figure 3: Performance (simulated) of Several Codes on a 64 QAM System
ORDERING INFORMATION 64qam_oc3
PART NUMBER DESCRIPTION ABOUT AHA
155 Mbit/sec Turbo Product Comtech AHA Corporation (AHA) develops
AHA4540B-086 PQC Code Encoder/Decoder - and markets superior integrated circuits, boards,
and intellectual property core technology for
Commercial Temp communications systems architects worldwide.
AHA has been setting the standard in Forward Error
155 Mbit/sec Turbo Product Correction and Lossless Data Compression
AHA4540B-086 PQI Code Encoder/Decoder - technology for many years and provides flexible,
cost-effective solutions for today’s growing
Industrial Temp bandwidth and reliability challenges. Comtech
AHA Corporation is a wholly owned subsidiary of
Comtech Telecommuncations Corp. (NASDAQ:
CMTL). For more information, visit www.aha.com.
155 MBITS/SEC TURBO PRODUCT CODE
ENCODER/DECODER
The AHA4540 device is a single-chip Turbo FEATURES
Product Code (TPC) Forward Error Correction
(FEC) Encoder/Decoder capable of 155 Mbit/sec PERFORMANCE:
(OC-3) data rates (up to 200 Mbit/sec channel rates).
This device integrates both a TPC encoder and ? Maximum 200 Mbit/sec channel rate
decoder, and can be operated in a full duplex mode. ? Payload data rates of at least 155 Mbit/sec for
In addition to TPC coding, support is included for
helical interleaving, synchronization mark insertion code rates >0.7 and three iterations
and detection, CRC computation, scrambling, and ? Symbol rates up to 50 MSym/sec
higher order modulation symbol mapping. Figure 1 ? Encode Latency of less than 10 clocks
shows the functional BLOCK diagram. ? Integrated encoder/decoder;
The channel interface supports direct scrambler/descrambler; and
connection to various modulators and demodulators. interleaver/deinterleaver for full duplex operation
Support for an arbitrary constellation mapping is ? Supports enhanced Turbo Product Codes (eTPCs)
included with external logic. ? Corrections count and averaging for channel SNR
estimation
The encode path accepts byte-wide data,
computes and inserts a CRC, and scrambles the data FLEXIBILITY:
before TPC encoding. After the error correction
code (ECC) bits are inserted by the encoder, the data ? Code Rates from .25 to 0.98
is helically interleaved, and block synchronization ? Variable iterations up to 256 per block
marks are inserted to assist the decoder. Finally, the ? Block Sizes from 256 bits to 16 Kbits
data is mapped according to the constellation and ? Programmable code shortening supports exact
output from the device.
block sizes
The decoder accepts input symbols via the ? 32 bit CRC Insertion and Checking with
demodulated in-phase (I) and quadrature (Q)
components or alternately as soft metric inputs from programmable packet length
an external demodulator. An internal block
synchronizer searches for synchronization marks, CHANNEL INTERFACE:
rotating the input symbol phase as necessary. After
synchronization is achieved, the data is helically ? Accepts in-phase and quadrature (I & Q) inputs,
deinterleaved and decoded by the TPC decoder. The up to 8 bits each
output of the decoder is descrambLED, and the CRC
is computed to verify data integrity. Decoded data is ? Supports soft metric inputs at up to 4 soft metrics
output in a parallel, byte-wide fashion. of 4 bits each
Internal circuitry enables the transfer rate across ? Soft metric computation for BPSK, QPSK, 8-
all ports, generating a constant, non-burst data flow. PSK, 16-QAM, 64-QAM, and 256-QAM
In addition, control of an external VCO can be used
to generate data clocks, greatly simplifying system ? Supports additional modulation formats with
clocking issues. external logic
comtech aha corporation ? Encoder and decoder pass through modes
? Programmable packet and block level
synchronization
? Automatic phase ambiguity resolution
? Supports insertion and detection of sync marks up
to 32 bits in length
? 8-bit Parallel Data Input/Output
? Support for external VCO to generate data clocks
OTHERS:
? Intel or Motorola microprocessor interface
? 3.3V I/O, 1.8V core operation
? Commercial or industrial temperature rating
? RoHS compliant
This product is covered under multiple patents held or licensed by Comtech AHA Corp.
This product is covered by a Turbo Code Patent License from France Telecom - TDF -
Groupe des ecoles des telecommunications.
*Request the AHA4540B Product Specification for complete details.
comtech aha corporation
CODE TYPES
Table 1 shows a partial list of the codes supported by this product. Note that this is not a complete list
of base codes. In addition, each of the codes listed can be shortened to achieve smaller block size with only
minor changes to code rate.
Table 1: Partial Code List
CODE BLOCK SIZE DATA SIZE RATE CODING GAIN # ITERATIONS
AT 155 mBPS
(X)x(Y)x(Z) (bits) (bits) (dB)
(128,127)x(128,126)+ 16384 16002 0.977 4.3 4
(128,120)x(128,126)+
(128,120)x(128,120) 16384 15120 0.923 5.5 5
(64,57)x(16,15)x(16,15)
(128,127)x(64,62)+ 16384 14400 0.879 6.5 6
(128,120)x(64,62)+
(128,120)x(64,57) 16384 12825 0.783 6.9 4
(32,26)x(16,15)x(16,15)
(64,63)x(64,62)+ 8192 7874 0.961 4.4 4
(64,57)x(64,57)
(64,63)x(32,30)+ 8192 7440 0.908 5.5 4
(64,57)x(32,26)
(32,26)x(32,26) 8192 6840 0.84 6.5 5
8192 5850 0.714 7.2 4
4096 3906 0.954 4.5 3
4096 3249 0.793 6.9 4
2048 1890 0.923 4.5 3
2048 1482 0.724 6.9 3
1024 676 0.660 6.3 2
+ enhanced TPC (includes hyper diagonal axis).
Figure 1: Turbo Product Code Encoder/Decoder
ENCODER
ENC_DATA CRC Scrambler TPC Helical Sync Constellation XMIT_DATA
Insertion Encoder Interleaver
Insertion Mapper
DECODER
DEC_DATA CRC Descrambler TPC Helical Sync Soft REC_DATA
Verification Decoder Deinterleaver Detection Metric
Computation
uP_INT Microprocessor Interface,
Control and Status
Registers AHA4540
comtech aha corporation
FUNCTIONAL OVERVIEW
The channel encoder is designed to input data in When using internal soft metric computation,
a byte-wide fashion. This data is CRC encoded and the input data is an I and Q sample value for the
randomized before coding by the TPC encoder. given symbol. The soft metric computation engine
Synchronization marks are then inserted into the converts each I and Q sample to the soft metrics
data before it is mapped to a user programmable required by the TPC decoder.
constellation. The blocks may be bypassed if not
needed. When soft metric computation is disabled, the
input data is a soft metric value for each bit in the
Each symbol for modulation is output TPC block with up to 4 bits transferred on each
synchronous to the transmit clock, with one symbol clock edge. Each bit would consist of up to 4
transferred for each rising edge of the clock. The confidence bits per data bit. If enabled, all
format for output data depends on the modulation synchronization is controlled by the device
format chosen. including phase ambiguity resolution. Output is in a
byte wide fashion with packet start, end and error
The channel decode data path begins with signals.
received symbols input to the device synchronous to
the receive clock, with one symbol transferred per
rising edge.
CODE PERFORMANCE
Figure 2: Bit Error Rate (BER) Performance (simulated) on a QPSK Channel
bpsk_oc3
comtech aha corporation
Figure 3: Performance (simulated) of Several Codes on a 64 QAM System
ORDERING INFORMATION 64qam_oc3
PART NUMBER DESCRIPTION ABOUT AHA
155 Mbit/sec Turbo Product Comtech AHA Corporation (AHA) develops
AHA4540B-086 PQC Code Encoder/Decoder - and markets superior integrated circuits, boards,
and intellectual property core technology for
Commercial Temp communications systems architects worldwide.
AHA has been setting the standard in Forward Error
155 Mbit/sec Turbo Product Correction and Lossless Data Compression
AHA4540B-086 PQI Code Encoder/Decoder - technology for many years and provides flexible,
cost-effective solutions for today’s growing
Industrial Temp bandwidth and reliability challenges. Comtech
AHA Corporation is a wholly owned subsidiary of
Comtech Telecommuncations Corp. (NASDAQ:
CMTL). For more information, visit www.aha.com.
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