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參數(shù)資料
| 型號(hào)： | PS0T03LC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ULTRA LOW CAPACITANCE TVS ARRAY |
| 中文描述： | 超低電容二極管陣列 |
| 文件頁(yè)數(shù)： | 4/5頁(yè) |
| 文件大?。?/td> | 175K |
| 代理商： | PS0T03LC |
4
www.protekdevices.com
05066.R4 8/03
PSOT03LC
thru
PSOT36LC
APPLICATION NOTE
The PSOTxxLC Series are low capacitance TVS arrays designed to protect I/O or data lines from the damaging effects of ESD or EFT. This product
series provides unidirectional & bidirectional protection, with a surge capability of 500 Watts P
PP
per line for an 8/20μs waveform and ESD protection >
40 kilovolts.
BIDIRECTIONAL COMMON-MODE CONFIGRUATION (Figure 1)
Two PSOTxxLC devices, when used in paralell, provide protection in a
common-mode configuration as depicted in Figure 1.
Circuit connectivity is as follows:
I/O Line is connected to Device 1, Pin 1.
I/O Line is connect to Device 2, Pin 2.
Device 1, Pin 2 is connected to ground.
Device 2, Pin 1 is connected to ground.
Device 1 & 2, Pin 3 is not connected.
BIDIRECTIONAL DIFFERENTIAL-MODE CONFIGRUATION (Figure
1)
In addition, two PSOTxxLC devices, when used in paralell, provide
protection in a differential-mode configuration for Ethernet applications as
depicted in Figure 2.
Circuit connectivity is as follows:
I/O Line 1 is connected to Device 1, Pin 1.
I/O Line 1 is connect to Device 2, Pin 2.
I/O Line 2 is connected to Device 1, Pin 1.
I/O Line 2 is connect to Device 2, Pin 2.
Device 1 & 2, Pin 3 is not connected.
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Circuit board layout is critical for Electromagnetic
Compatibility (EMC) protection. The following
guidelines are recommended:
The protection device should be placed near the
input terminals or connectors, the device will
divert the transient current immediately before it
can be coupled into the nearby traces.
The path length between the TVS device and the
protected line should be minimized.
All conductive loops including power and ground
loops should be minimized.
The transient current return path to ground
should be kept as short as possible to reduce
parasitic inductance.
Ground planes should be used whenever
possible. For multilayer PCBs, use ground vias.
Figure 1 - Common-Mode I/O Port Protection
3
1
2
3
1
2
I/O LINE
GND
Figure 2 - Differential-Mode Ethernet Protection
3
1
2
3
1
2
I/O 1
I/O 2
E
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