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參數(shù)資料
| 型號： | PS4066ESD |
| 英文描述： | SPST Analog Switch |
| 中文描述： | SPST模擬開關(guān) |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 566K |
| 代理商： | PS4066ESD |
5
PS8184A 10/15/98
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PS4066/PS4066A
Low-Cost, Quad, SPST, CMOS Analog Switches
Electrical Specifications - Single +3V Supply
(V+ = +2.7V to 3.3V, GND = 0V, V
I
NH
= 2.4V, V
INL
= 0.8V)
r
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0
+
V
V
e
a
R
-
O
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a
C
R
N
O
I
3
V
O
N
=
+
V
M
5
O
C
=
,
A
m
1
V
=
5
2
0
7
1
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F
5
2
2
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a
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-
O
-
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t
N
O
V
,
3
=
+
V
O
N
V
5
=
5
2
l
F
2
0
8
5
0
0
8
3
5
1
2
1
s
e
m
i
-
O
-
T
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)
F
O
(
V
,
3
=
+
V
O
N
V
5
=
5
0
4
l
F
0
0
2
n
o
e
C
)
Q
C
L
V
=
,
n
1
R
G
=
N
V
E
0
G
,
0
=
N
E
5
2
2
0
1
C
p
y
p
u
S
t
e
C
y
p
u
S
e
P
+
V
,
a
c
3
l
=
+
V
N
I
,
V
r
f
V
0
r
=
o
n
s
n
l
F
1
1
0
0
1
μ
A
Notes:
1. The algebraic convention, where the most negative value is a minimum and the most positive is a maximum, is used in
this data sheet.
2. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing.
3. Guaranteed by design
4.
R
ΟΝ
=
R
ΟΝ
max
-
R
ΟΝ
min
5. Flatness is defined as the difference between the maximum and minimum value of on-resistance measured.
6. Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at +25oC.
7. Off Isolation = 20log
10
[ V
COM
/ (V
NO
or V
NO
)
], V
COM
= 0utput, V
NC
/V
NO
=
input to off switch
8. Between any two switches.
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