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參數(shù)資料
| 型號(hào)： | PS48M2TF3 |
| 元件分類(lèi)： | 電源模塊 |
| 英文描述： | 1-OUTPUT DC-DC REG PWR SUPPLY MODULE |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大小： | 260K |
| 代理商： | PS48M2TF3 |
+Sense from
other modules
in the array
+OUT
+S
SC
-S
-OUT
Figure 12—OR’ing diodes connections.
Load
+S
–S
PowerStick
2
PowerStick
1
PowerStick
N+1
+OUT
+S
SC
-S
-OUT
+OUT
+S
SC
-S
-OUT
+OUT
+S
SC
-S
-OUT
Figure 11—N+1 module array output connections.
CONTROL FUNCTIONS - PR PIN
Parallel Operation
The PR pin supports paralleling for increased power with N+1
(N+M) redundancy and phased array capability (see Phased
Array Control Chip at vicr.com). Modules of the same input
voltage, output voltage, and power level will current share if
all PR pins are suitably interfaced.
Compatible interface architectures include the following:
DC coupled single-wire interface. All PR pins are directly
connected to one another. This interface supports current
sharing but is not fault tolerant. Minus In pins must be tied to
the same electric potential. See Figure 9.
AC coupled single-wire interface. All PR pins are connected
to a single communication bus through .001F (500V)
capacitors. This interface supports current sharing and is fault
tolerant except for the communication bus. See Figure 10.
Vicor Corporation Tel: 800-735-6200 978-470-2900 Fax: 978-475-6715
Page 6
For the most current data and applications support, visit vicr.com.
Figure 9—DC coupled single-wire interface.
PowerStick 2
(up to 12)
PowerStick
1
Ground plane
+IN
PC
PR
-IN
+IN
PC
PR
-IN
PowerStick 2
(up to 12)
PowerStick
1
Ground plane
.001
F
.001
F
+IN
PC
PR
-IN
+IN
PC
PR
-IN
Figure 10—AC coupled single-wire interface.
The +Out and –Out power buses
should be designed to minimize
and balance parasitic impedance
from each module output to the
load.
The +Sense pins should be tied
to the same point on the +Out
power bus; the –Sense pins
should be tied to the same point
on the –Out power bus.
At the discretion of the power
system designer, a subset of all
modules within an array may be
configured as slaves by shorting
SC to –S.
OR’ing diodes may be inserted in
series with the +Out pins of each
module to provide module output
fault tolerance.
PR ELIMINAR Y
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