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參數(shù)資料
| 型號(hào)： | PSC5A10-9LIRPCD |
| 元件分類(lèi)： | 電源模塊 |
| 英文描述： | 1-OUTPUT DC-DC REG PWR SUPPLY MODULE |
| 文件頁(yè)數(shù)： | 2/11頁(yè) |
| 文件大?。?/td> | 236K |
| 代理商： | PSC5A10-9LIRPCD |
PSC-Family
Switching Regulators, PCB & Chassis
Industrial Environment
4 - 62
Edition 2/96 - Melcher AG
MELCHER
The Power Partners.
4.2
Application examples
a) The signal
UD can be utilized in battery powered systems to provide a warning in case of low batteries.
b) In case of power failure, the signal can serve to initiate data save routines.
Option D (“Save Data”, input undervoltage monitor)
Note: Output instead of input undervoltage monitor is
available on request (Option D1).
If the input voltage
Ui is below the adjustable threshold volt-
age
Ut, the control circuit for terminal D has low impedance.
Terminal D and Go– are connected to a self-conducting
field effect transistor (FET). A 0.5 W Zener diode provides
protection against overvoltages.
Fig. 10
Test circuit with definition of voltage UD and current ID on
Terminal D.
Fig. 11
Definition of Ut and UH
Vi +
Gi –
Go –
8.2 V
D
UD
+5 V
100 pF
ID
10 k
FET
Ut
UD
UD high
UD low
Ut
Ui
UH
Data
Table 10: Option D data
Characteristics
Conditions
PSC
Unit
min
typ
max
UD low
Voltage - Terminal D at low impedance
Ui < Ut, ID ≤ 2.5 mA
0.8
V
UD high
Voltage - Terminal D at high impedance
Ui > Ut + UH, ID > 25 A
4.75
tlow min
Minimum duration
UD low
30
ms
tD f
Response time to
UD low
1
s
ID max
Maximum current - Terminal D
20
mA
The voltage
Ut can be externally adjusted with a trim poten-
tiometer by means of a screwdriver. The hysteresis
UH of
Ut is <2%. Terminal D stays low for a minimum time
tlow min, in order to prevent any oscillation. Ut can be set to a
value between
Ui min and Ui max. It is important to note that
the FET can become conductive again when
UD > Ui – 3V.
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