參數(shù)資料
型號(hào): PSD301-B-70L
廠商: 意法半導(dǎo)體
英文描述: Low Cost Field Programmable Microcontroller Peripherals
中文描述: 低成本現(xiàn)場可編程微控制器外圍設(shè)備
文件頁數(shù): 43/85頁
文件大小: 691K
代理商: PSD301-B-70L
PSD3XX Famly
40
-70
-90*
-15
CMiser
On =
Add
Turbo
Of =
Add
Symbol
Parameter
Unit
Min
Max
Min
Max
Min
Max
T1
ALE or AS Pulse Width
18
20
40
0
0
ns
T2
Address Set-up Time
5
5
12
0
0
ns
T3
Address Hold Time
7
8
10
0
0
ns
T4
Leading Edge of Read
to Data Active
0
0
0
0
0
ns
T5
ALE Valid to Data Valid
80
100
160
10
0
ns
T6
Address Valid to Data Valid
70
90
150
10
0
ns
T7
CSI Active to Data Valid
80
100
160
10
0
ns
T8
Leading Edge of Read
to Data Valid
20
32
55
0
0
ns
Leading Edge of Read to
Data Valid in 8031-Based
Architecture Operating with
PSEN and RD in Separate
Mode
T8A
32
32
55
0
0
ns
T9
Read Data Hold Time
0
0
0
0
0
ns
T10
Trailing Edge of Read to
Data High-Z
20
32
35
0
0
ns
Trailing Edge of ALE or AS
to Leading Edge of Write
T11
0
0
0
0
0
ns
T12
RD, E, PSEN, or DS Pulse Width
35
40
60
0
0
ns
T12A
WR Pulse Width
18
20
35
0
0
ns
Trailing Edge of Write or Read
to Leading Edge of ALE or AS
T13
5
5
5
0
0
ns
T14
Address Valid to Trailing Edge
of Write
70
90
150
0
0
ns
CSI Active to Trailing Edge
of Write
T15
80
100
160
0
0
ns
T16
Write Data Set-up Time
18
20
30
0
0
ns
T17
Write Data Hold Time
5
5
10
0
0
ns
T18
Port to Data Out Valid
Propagation Delay
25
30
35
0
0
ns
T19
Port Input Hold Time
0
0
0
0
0
ns
T20
Trailing Edge of Write to Port
Output Valid
30
40
50
0
0
ns
T21
ADi
1
or Control to CSOi
2
Valid
6
20
6
25
6
35
0
10
ns
T22
ADi
1
or Control to CSOi
2
Invalid
5
20
5
25
4
35
0
10
ns
18.7 Timng Parameters – PSD3XX/ZPSD3XX (All 5 V devices)
*
-90 speed available only on Industrial Temperature versions.
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