- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376249 > PSD312R-70J (意法半導(dǎo)體) CABLE ASSEMBLY; C MALE TO C MALE; 50 OHM, RG223/U COAX, DOUBLE SHIELDED PDF資料下載
參數(shù)資料
| 型號(hào)： | PSD312R-70J |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CABLE ASSEMBLY; C MALE TO C MALE; 50 OHM, RG223/U COAX, DOUBLE SHIELDED |
| 中文描述： | 低成本現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備 |
| 文件頁(yè)數(shù)： | 21/85頁(yè) |
| 文件大?。?/td> | 691K |
| 代理商： | PSD312R-70J |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)當(dāng)前第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)
PSD3XX Famly
18
10.
I/OPort
Functions
(
cont.)
10.3 Port B (PB0-PB7)
The control registers of Port B are located in CSIOPORT space; see Table 5A and 5B.
10.3.1 Port B (PB0-PB7) in Multiplexed Address/Data Mode
Each pin of Port B can be individually configured. The following table summarizes what the
control registers (in CSIOPORT space) for Port B do:
NOTE:
1. Default value is the value after reset.
Default
Value
(Note 1)
Register Name
0 Value
1 Value
Port B Pin Register
Sampled logic level
at pin = ‘0’
Pin is configured
as input
Data in DFF = ‘0’
Sampled logic level
at pin = ‘1’
Pin is configured
as output
Data in DFF = ‘1’
X
Port B Direction Register
0
Port B Data Register
0
MCUI/OMode
The default configuration of Port B is MCU I/O. In this mode, every pin can be set
(at run-time) as an input or output by writing to the respective pin’s direction flip-flop (DIR
FF, Figure 6). As an output, the pin level can be controlled by writing to the respective pin’s
data flip-flop (DFF, Figure 6). The Pin Register can be read to determine logic level of the
pin. The contents of the Pin Register indicate the true state of the PSD driving the pin
through the DFF or an external source driving the pin. Pins can be configured as CMOS
or open-drain using
ST
’s PSDsoft software. Open-drain pins require external pull-up
resistors.
Chip Select Output
Alternatively, each bit of Port B can be configured to provide a chip-select output signal
from PAD B. PB0-PB7 can provide CS0-CS7, respectively. The functionality of these pins is
not limited to chip selects only; they can be used for generic combinatorial logic as well.
Each of the CS0-CS3 signals is comprised of four product terms, and each of the CS4-CS7
signals is comprised of two product terms.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD312R-70JI | Low Cost Field Programmable Microcontroller Peripherals |
| PSD312R-70JM | Low Cost Field Programmable Microcontroller Peripherals |
| PSD312R-90JI | Low Cost Field Programmable Microcontroller Peripherals |
| PSD312R-90JM | Low Cost Field Programmable Microcontroller Peripherals |
| PSD313V-70JI | Low Cost Field Programmable Microcontroller Peripherals |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD312R-70JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD312R-70JM | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD312R-90J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD312R-90JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD312R-90JM | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。