參數(shù)資料
型號: PSD312R-90JI
廠商: 意法半導體
英文描述: Low Cost Field Programmable Microcontroller Peripherals
中文描述: 低成本現(xiàn)場可編程微控制器外圍設(shè)備
文件頁數(shù): 45/85頁
文件大小: 691K
代理商: PSD312R-90JI
PSD3XX Famly
42
-15*
-20
-25
CMiser
On =
Add
Turbo
Of =
Add
Symbol
Parameter
Unit
Min
Max
Min
Max
Min
Max
T1
ALE or AS Pulse Width
40
50
60
0
0
ns
T2
Address Set-up Time
12
15
20
0
0
ns
T3
Address Hold Time
10
15
20
0
0
ns
T4
Leading Edge of Read
to Data Active
0
0
0
0
0
ns
T5
ALE Valid to Data Valid
170
200
250
20
0
ns
T6
Address Valid to Data Valid
150
200
250
20
0
ns
T7
CSI Active to Data Valid
160
200
250
20
0
ns
T8
Leading Edge of Read
to Data Valid
45
50
60
0
0
ns
Leading Edge of Read to
Data Valid in 8031-Based
Architecture Operating with
PSEN and RD in Separate
Mode
T8A
65
70
80
0
0
ns
T9
Read Data Hold Time
0
0
0
0
0
ns
T10
Trailing Edge of Read to
Data High-Z
45
50
55
0
0
ns
Trailing Edge of ALE or AS
to Leading Edge of Write
T11
0
0
0
0
0
ns
T12
RD, E, PSEN, or DS Pulse Width
60
75
85
0
0
ns
T12A
WR Pulse Width
35
45
55
0
0
ns
Trailing Edge of Write or Read
to Leading Edge of ALE or AS
T13
5
5
5
0
0
ns
T14
Address Valid to Trailing Edge
of Write
150
200
250
0
0
ns
CSI Active to Trailing Edge
of Write
T15
160
200
250
0
0
ns
T16
Write Data Set-up Time
30
40
50
0
0
ns
T17
Write Data Hold Time
10
12
15
0
0
ns
T18
Port to Data Out Valid
Propagation Delay
45
50
60
0
0
ns
T19
Port Input Hold Time
0
0
0
0
0
ns
T20
Trailing Edge of Write to Port
Output Valid
50
60
70
0
0
ns
T21
ADi
1
or Control to CSOi
2
Valid
6
50
5
55
5
60
0
20
ns
T22
ADi
1
or Control to CSOi
2
Invalid
4
50
4
55
4
60
0
20
ns
18.8 Timng Parameters – ZPSD3XXV (3 V devices only)
*
-15 speed available only on ZPSD311V.
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