參數(shù)資料
型號: PSD401A1-70U
英文描述: Field-Programmable Peripheral
中文描述: 現(xiàn)場可編程外圍
文件頁數(shù): 76/123頁
文件大小: 657K
代理商: PSD401A1-70U
PSD4XX Famly
73
12.0
System
Configuration
Table 21. Register Address Ofset
Table 21a. Register Address Ofset
(For 16-bit Motorola Microcontrollers in 16-bit mode. Use Table 21 if 8-bit mode is selected.)
Register
Name
Address
Ofset
Register
Name
Address
Ofset
PAGE REGISTER
E1
VM
C1
PMMR1
B0
PMMR0
B1
The CSIOP signal, which is generated by the DPLD, selects the internal I/O devices or
registers. The CSIOP signal takes up 256 bytes of address space and is defined by the
user in the PSDSoft Software. The following is an address offset map for the various
devices relative to the CSIOP base address.
Some Motorola 16-bit microcontrollers have a different data bus/data byte orientation. This
requires a different address offset for the internal PSD4XX I/O devices or registers. Tables
21a and 22a in this section are for this group of microcontrollers which include the
M68HC16, M68302 and M683XX.
Register
Name
Address
Ofset
Register
Name
Address
Ofset
PAGE REGISTER
E0
VM
C0
PMMR1
B1
PMMR0
B0
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