參數(shù)資料
型號: PSD401A1-90U
英文描述: Field-Programmable Peripheral
中文描述: 現(xiàn)場可編程外圍
文件頁數(shù): 93/123頁
文件大?。?/td> 657K
代理商: PSD401A1-90U
PSD4XX Famly
90
-20
-25
ZPLD_TURBO
OFF
*
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
Maximum Frequency
External Feedback
1/(t
SA
+ t
COA
)
14.49
11.11
MHz
Maximum Frequency
Internal Feedback (f
CNTA
)
1/(t
SA
+t
COA
–10)
(Note 1)
16.95
12.50
MHz
f
MAXA
Maximum Frequency
Pipelined Data
1/(t
CH
+ t
CL
)
31.25
18.52
MHz
t
SA
Input Setup Time
Any Input
13
30
Add 20
ns
t
HA
Input Hold Time
Any Input
13
30
0
ns
t
CHA
Clock High Time
Any Input
25
27
0
ns
t
CLA
Clock Low Time
Any Input
16
27
0
ns
t
COA
Clock to Output Delay
Any Input to Port B
56
60
Add 20
ns
t
ARD
Array Delay for Product
Term Expansion
Any Macrocell
33
35
0
ns
t
MINA
Minimum Clock Period
1/f
CNT
59
80
0
ns
Asynchronous Clock Mode
(3.0 V ± 10%, Note 1)
AC/DC Parameters – ZPLDTimng Parameters (ZPSD4XXV Versions)
(3.0 V ± 10%)
NOTE:
1.
Only Port B has asynchronous outputs. Clock into macrocell Flip Flop is generated by a product term.
*
If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 20 ns to the timing parameters.
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