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| 型號(hào)： | PSD401A2 |
| 英文描述： | PSD4XX/ZPSD4XX FAMILY FIELD-PROGRAMMABLE MICROCONTROLLER PERIPHERALS |
| 中文描述： | PSD4XX/ZPSD4XX家庭領(lǐng)域，可編程微控制器外設(shè) |
| 文件頁(yè)數(shù)： | 79/123頁(yè) |
| 文件大?。?/td> | 657K |
| 代理商： | PSD401A2 |
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Port Configuration
Reset
Stand-by Mode
Port I/O
Input
Unchanged
ZPLD Output
Active
Depend on Inputs to the ZPLD
Address Out
Tri-stated
Not Defined
Data Port
Tri-stated
Tri-stated
Peripheral I/O
Tri-stated
Tri-stated
PSD4XX Famly
76
Register Name
Device
Reset State
Control
Port A, B, C, D, E
Set to “0”
(Address Out Mode)
Data Out
(data or address)
Port A, B, C, D, E
Set to “0”
Direction
Port A, B, C, D, E
Set to “0” – Input Mode
Open Drain
Port C, D
Set to “0” – CMOS Outputs
Page Register
Page Logic
Set to “0”
PMMR0, PMMR1
Power Management Unit
Set to “0”
VM
Volatile Memory
Set to “0”
System
Configuration
(cont.)
Table 24. Registers Reset Values
Table 25. I/OPin Status During Reset and Standby Mode
12.1 Reset Input
The reset input to the PSD4XX (RESET) is an active low signal which resets some of the
internal devices and configuration registers. The Timing Diagram in the AC/DC
characterization section shows the reset signal timing requirement. The active low range
has a minimum T1 duration. After the rising edge of RESET, the PSD4XX remains in
reset during T2 range. (See Figure 48). The PSD4XX must be reset at power up before it
can be used.
12.2 ZPLDand Memory During Reset
While the Reset Input is active, the ZPLD generates outputs as defined in the PSDabel
equations. The EPROM and SRAM blocks respond to the microcontroller bus cycle during
reset, but the data is not guaranteed.
12.3 Register Values During and After Reset
Table 24 summarizes the status of the volatile register values during and after reset.
The default values of the volatile registers are “0” after reset.
12.4 ZPLDMacrocell Initialization
The D flip flops in the macrocells in the GPLD can be cleared by:
J
A product term (.RE) defined by the user in PSDabel, or
J
The MACRO-RST (Reset) input, enabled and defined in PSDabel.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD401A2-12J | Field-Programmable Peripheral |
| PSD401A2-12JI | Field-Programmable Peripheral |
| PSD401A2-12LI | Field-Programmable Peripheral |
| PSD401A2-12U | Field-Programmable Peripheral |
| PSD401A2-12UI | Field-Programmable Peripheral |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD401A2-12J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD401A2-12JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD401A2-12LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD401A2-12U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD401A2-12UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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