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參數(shù)資料
| 型號： | PSD402A1-12LI |
| 英文描述： | Field-Programmable Peripheral |
| 中文描述： | 現(xiàn)場可編程外圍 |
| 文件頁數(shù)： | 64/123頁 |
| 文件大小： | 657K |
| 代理商： | PSD402A1-12LI |
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PSD4XX Famly
61
9.4 Memory Block
The PSD4XX provides EPROM memory for code storage and SRAM memory for scratch
pad usage. Chip selects for the memory blocks come from the DPLD decoding logic and
are defined by the user in the PSDsoft Software. Figure 32 shows the organization of the
Memory Block.
The PSD4XX family uses Zero-power memory techniques that place memory into Standby
Mode between MCU accesses. The memory becomes active briefly after an address
transition, then delivers new data to the outputs, latches the outputs, and returns to standby.
This is done automatically and the designer has to do nothing special to benefit from this
feature. Both the EPROM and SRAM have this feature.
9.4.1 EPROM
The PSD4XX provides three EPROM densities: 256Kbit, 512Kbit, or 1Mbit. The EPROM
is divided into four 8K, 16K or 32K byte blocks. Each block has its own chip select signals
(ES0 – ES3). The EPROM can be configured as 32K x 8, 64K x 8 or 128K x 8 for
microcontrollers with an 8-bit data bus. For 16-bit data buses, the EPROM is configured as
16K x 16, 32K x 16 or 64K x 16.
9.4.2 SRAM
The SRAM has 16Kbits of memory, organized as 2K x 8 or 1K x 16. The SRAM is enabled
by chip select signal RS0 from the DPLD. The SRAM has a battery back-up (STBY) mode.
This back-up mode is invoked when the V
CC
voltage drops under the Vstdby voltage by
approximately 0.7 V. The Vstdby voltage is connected only to the SRAM and cannot be
lower than 2.7 volts.
9.4.3 Memory Select Map
The EPROM and SRAM chip select equations are defined in the ABEL file in terms of
address and other DPLD inputs. The memory space for the EPROM chip select
(ES0 – ES3) should not be larger than the EPROM block (8KB, 16KB, or 32KB) it is
selecting.
The following rules govern how the internal PSD4XX memory selects/space are defined:
J
The EPROM blocks address space cannot overlap
J
SRAM, internal I/O and Peripheral I/O space cannot overlap
J
SRAM, internal I/O and Peripheral I/O space can overlap EPROM space, with
priority given to SRAM or I/O. The portion of EPROM which is overlapped
cannot be accessed.
The Peripheral I/O space refers to memory space occupied by peripherals when Port A is
configured in the Peripheral I/O Mode.
The PSD4XX
Architecture
(cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD402A1-12U | Field-Programmable Peripheral |
| PSD402A1-12UI | Hi-Rel Adjustable Voltage 3-Terminal Negative Regulator; Qualified Part Number similar to OM1322NKM |
| PSD402A1-15J | Hi-Rel Adjustable Voltage 3-Terminal Positive Regulator; Qualified Part Number similar to OM1321NKM |
| PSD402A1-15JI | Hi-Rel Adjustable Voltage 3-Terminal Negative Regulator; Qualified Part Number similar to OM1323N2M |
| PSD402A1-15LI | Hi-Rel Adjustable Voltage 3-Terminal Negative Regulator; Qualified Part Number similar to OM1325SMM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD402A1-12U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD402A1-12UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD402A1-15J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD402A1-15JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD402A1-15LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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