參數(shù)資料
型號(hào)： PSD402A1-15LI
英文描述： Hi-Rel Adjustable Voltage 3-Terminal Negative Regulator; Qualified Part Number similar to OM1325SMM
中文描述： 現(xiàn)場(chǎng)可編程外圍
文件頁(yè)數(shù)： 2/123頁(yè)
文件大小： 657K
代理商： PSD402A1-15LI
第1頁(yè)當(dāng)前第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)
i
PSD4XX Famly
PSD4XX/ZPSD4XX
Field-Programmable Microcontroller Peripherals
Table of Contents
1
2
3
4
5
6
7
8
9
Introduction...........................................................................................................................................................1
Key Features ........................................................................................................................................................2
Notation ................................................................................................................................................................3
Zero-Power Background.......................................................................................................................................3
Integrated Power Management
TM
Operation........................................................................................................5
Design Flow..........................................................................................................................................................6
PSD4XX Family....................................................................................................................................................7
Table 2. PSD4XX Pin Descriptions......................................................................................................................8
The PSD4XX Architecture ..................................................................................................................................10
9.1 The ZPLD Block..........................................................................................................................................10
9.1.1 The PSD4XXA1 ZPLD Block............................................................................................................10
9.1.1.1
The DPLD ..........................................................................................................................12
9.1.1.2
The GPLD..........................................................................................................................13
9.1.1.3
TPA Macrocell Structure...................................................................................................13
9.1.1.4
Port B Macrocell Structure.................................................................................................17
9.1.1.5
The ZPLD Power Management..........................................................................................18
9.1.2 The PSD4XXA2 ZPLD Block............................................................................................................22
9.1.2.1
The DPLD ..........................................................................................................................24
9.1.2.2
The GPLD..........................................................................................................................26
9.1.2.3
Port A Macrocell Structure.................................................................................................26
9.1.2.4
Port B Macrocell Structure.................................................................................................30
9.1.2.5
Port E Macrocell Structure.................................................................................................33
9.1.2.6
The ZPLD Power Management..........................................................................................34
9.2 Bus Interface...............................................................................................................................................37
9.2.1 Bus Interface Configuration..............................................................................................................37
9.2.2 PSD4XX Interface to a Multiplexed Bus...........................................................................................38
9.2.3 PSD4XX Interface to Non-Multiplexed Bus......................................................................................38
9.2.4 Data Byte Enable..............................................................................................................................42
9.2.5 Optional Features.............................................................................................................................43
9.2.6 Bus Interface Examples....................................................................................................................43
9.3 I/O Ports......................................................................................................................................................48
9.3.1 Standard MCU I/O............................................................................................................................48
9.3.2 PLD I/O ...........................................................................................................................................48
9.3.3 Address Out......................................................................................................................................49
9.3.4 Address In ........................................................................................................................................49
9.3.5 Data Port ..........................................................................................................................................49
9.3.6 Alternate Function In ........................................................................................................................49
9.3.7 Peripheral I/O ...................................................................................................................................50
9.3.8 Open Drain Outputs..........................................................................................................................50
9.3.9 Port Registers...................................................................................................................................51
9.3.10 Port A – Functionality and Structure.................................................................................................54
9.3.11 Port B – Functionality and Structure.................................................................................................54
9.3.12 Port C and Port D – Functionality and Structure ..............................................................................57
9.3.13 Port E – Functionality and Structure.................................................................................................57
9.4 Memory Block.............................................................................................................................................61
9.4.1 EPROM ............................................................................................................................................61
9.4.2 SRAM...............................................................................................................................................61
相關(guān)PDF資料
PDF描述
PSD402A1-15U Hi-Rel Adjustable Voltage 3-Terminal Negative Regulator; Qualified Part Number similar to OM1322SMM
PSD402A1-15UI Hi-Rel Adjustable Voltage 3-Terminal Negative Regulator; A OM1322SMM with Standard Packaging
PSD402A1-20J Field-Programmable Peripheral
PSD402A1-20JI 30V Hi-Rel Synchronous Rectifier N-Channel MOSFET in a SMD-2 package; A IRHSNA57Z60 with Standard Packaging
PSD402A1-20LI -100V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a 18-pin LCC package; Similar to IRHE9130 with optional Total Dose Rating of 300kRads
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD402A1-15U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD402A1-15UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD402A1-20J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD402A1-20JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD402A1-20LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*